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MC68HC08JB1
Technical Data
M68HC08
Microcontrollers
MC68HC08JB1/D Rev. 2, 3/2002
WWW.MOTOROLA.COM/SEMICONDUCTORS
MC68HC08JB1
Technical Data
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Motorola and the Stylized M logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc.
(c) Motorola, Inc., 2002
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Technical Data
Technical Data 3
Technical Data
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.motorola.com/semiconductors/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History
Date Revision Level Description Corrected Figure 9-30 for USB module. Corrected timer discrepancies throughout Section 10. Timer Interface Module (TIM). 2 Added Table 11-1 . Port Control Register Bits Summary. Changed pullup resistor limits for D- and I/O ports in 16.6 DC Electrical Characteristics. 165 208 Page Number(s) 136 141
March, 2002
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MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Technical Data -- MC68HC08JB1
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 23 Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Section 3. Random-Access Memory (RAM) . . . . . . . . . . 45 Section 4. Read-Only Memory (ROM) . . . . . . . . . . . . . . . 47 Section 5. Configuration Register (CONFIG) . . . . . . . . . 49 Section 6. Central Processor Unit (CPU) . . . . . . . . . . . . 53 Section 7. Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . . 71 Section 8. System Integration Module (SIM) . . . . . . . . . 75 Section 9. Universal Serial Bus Module (USB) . . . . . . . . 95 Section 10. Timer Interface Module (TIM) . . . . . . . . . . . 141 Section 11. Input/Output Ports (I/O) . . . . . . . . . . . . . . . 163 Section 12. External Interrupt (IRQ) . . . . . . . . . . . . . . . 179 Section 13. Keyboard Interrupt Module (KBI). . . . . . . . 187 Section 14. Computer Operating Properly (COP) . . . . 197 Section 15. Low Voltage Inhibit (LVI) . . . . . . . . . . . . . . 203 Section 16. Electrical Specifications. . . . . . . . . . . . . . . 205 Section 17. Mechanical Specifications . . . . . . . . . . . . . 213
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List of Sections
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MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Technical Data -- MC68HC08JB1
Table of Contents
Section 1. General Description
1.1 1.2 1.3 1.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.1 Power Supply Pins (VDD, VSS) . . . . . . . . . . . . . . . . . . . . . . .27 1.5.2 Voltage Regulator Out (VREG) . . . . . . . . . . . . . . . . . . . . . . . 28 1.5.3 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . 29 1.5.4 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.5 External Interrupt Pins (IRQ, PTE4/D-) . . . . . . . . . . . . . . . .29 1.5.6 Port A Input/Output (I/O) Pins (PTA7/KBA7-PTA0/KBA0). .29 1.5.7 Port C I/O Pins (PTC0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.8 Port D I/O Pins (PTD0/1) . . . . . . . . . . . . . . . . . . . . . . . . . . .30 1.5.9 Port E I/O Pins (PTE4/D-, PTE3/D+, PTE1/TCH0) . . . . . . . 30
Section 2. Memory Map
2.1 2.2 2.3 2.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Section 3. Random-Access Memory (RAM)
3.1 3.2 3.3
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Table of Contents
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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Table of Contents Section 4. Read-Only Memory (ROM)
4.1 4.2 4.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Section 5. Configuration Register (CONFIG)
5.1 5.2 5.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Section 6. Central Processor Unit (CPU)
6.1 6.2 6.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .58 6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .60
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.7 6.8 6.9 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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Section 7. Oscillator (OSC)
7.1 7.2 7.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . . 72
7.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . 73 7.4.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . 73 7.4.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . 73 7.4.4 External Clock Source (OSCXCLK) . . . . . . . . . . . . . . . . . . . 73 7.4.5 Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 7.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Section 8. System Integration Module (SIM)
8.1 8.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 78 8.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.3.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . 78 8.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 79 8.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . . 79 8.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . 80 8.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . . 82 8.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . 83 8.4.2.6 Universal Serial Bus Reset . . . . . . . . . . . . . . . . . . . . . . . 83 8.4.2.7 Registers Values After Different Resets. . . . . . . . . . . . . . 84 8.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . 85
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8.5.2 8.5.3 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . . 85 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . .85
8.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.6.2 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . 90 8.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 8.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8.8.1 Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Section 9. Universal Serial Bus Module (USB)
9.1 9.2 9.3 9.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.5.1 USB Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.5.1.1 Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 9.5.1.2 Packet Identifier Field . . . . . . . . . . . . . . . . . . . . . . . . . .105 9.5.1.3 Address Field (ADDR) . . . . . . . . . . . . . . . . . . . . . . . . . .106 9.5.1.4 Endpoint Field (ENDP). . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.5.1.5 Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . . 106 9.5.1.6 End-of-Packet (EOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.5.2 Reset Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 9.5.3 Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.5.4 Resume After Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.5.4.1 Host Initiated Resume . . . . . . . . . . . . . . . . . . . . . . . . . .109 9.5.4.2 USB Reset Signalling. . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.5.4.3 Remote Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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9.5.5 9.6
Low-Speed Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
9.7 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.7.1 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.7.2 USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.7.2.1 Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . 112 9.7.2.2 Low Speed (1.5 Mbps) Driver Characteristics . . . . . . . . 112 9.7.2.3 Receiver Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.7.2.4 Data Source Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.7.2.5 Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . .114 9.7.3 USB Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.8.1 USB Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.8.2 USB Interrupt Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . .117 9.8.3 USB Interrupt Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . .118 9.8.4 USB Interrupt Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . .121 9.8.5 USB Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.8.6 USB Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.8.7 USB Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.8.8 USB Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.8.9 USB Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.8.10 USB Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.8.11 USB Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.8.12 USB Endpoint 0 Data Registers . . . . . . . . . . . . . . . . . . . . . 131 9.8.13 USB Endpoint 1 Data Registers . . . . . . . . . . . . . . . . . . . . . 132 9.8.14 USB Endpoint 2 Data Registers . . . . . . . . . . . . . . . . . . . . . 133 9.9 USB Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.9.1 USB End-of-Transaction Interrupt . . . . . . . . . . . . . . . . . . .134 9.9.1.1 Receive Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . . .135 9.9.1.2 Transmit Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . . 137 9.9.1.3 Transmit Endpoint 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.9.1.4 Transmit Endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.9.2 Resume Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.9.3 End-of-Packet Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
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Table of Contents Section 10. Timer Interface Module (TIM)
10.1 10.2 10.3 10.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 146 10.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . 147 10.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 147 10.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 148 10.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 149 10.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
10.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 10.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.8.1 TIM Clock Pin (PTE0/TCLK) . . . . . . . . . . . . . . . . . . . . . . . 153 10.8.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1) . . . . . . . 153 10.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 10.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . 154 10.9.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 10.9.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 157 10.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . .158 10.9.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Section 11. Input/Output Ports (I/O)
11.1 11.2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
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11.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 11.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 11.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.4 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.4.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.4.2 Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.5 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.5.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.5.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.6 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.6.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.6.2 Data Direction Register E. . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.7 Port Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.7.1 Port Option Control Register . . . . . . . . . . . . . . . . . . . . . . . 177
Section 12. External Interrupt (IRQ)
12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 PTE4/D- Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .183 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 184 IRQ Option Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . 185
Section 13. Keyboard Interrupt Module (KBI)
13.1 13.2 13.3
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Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
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13.4 13.5 13.6 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 13.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.8 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .193
13.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 13.9.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 193 13.9.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 195
Section 14. Computer Operating Properly (COP)
14.1 14.2 14.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
14.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.4.1 OSCXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 14.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 14.4.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 14.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 200 14.5 14.6 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 14.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 14.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
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Section 15. Low Voltage Inhibit (LVI)
15.1 15.2 15.3 15.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 LVI Control Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . 204
15.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 15.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 15.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Section 16. Electrical Specifications
16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .206 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 207 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 208 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 USB DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 210
16.10 USB Low-Speed Source Electrical Characteristics . . . . . . . . 211 16.11 USB Signaling Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 16.12 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . . 212
Section 17. Mechanical Specifications
17.1 17.2 17.3 17.4
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Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 20-Pin Dual In-Line Package (PDIP) . . . . . . . . . . . . . . . . . . .214 20-Pin Small Outline Integrated Circuit (SOIC) . . . . . . . . . . . 214
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List of Figures
Figure 1-1 1-2 1-3 1-4 2-1 2-2 5-1 6-1 6-2 6-3 6-4 6-5 6-6 7-1 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11
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Title
Page
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 20-pin PDIP/SOIC Pin Assignments. . . . . . . . . . . . . . . . . . . . . 27 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Regulator Supply Capacitor Configuration . . . . . . . . . . . . . . . .28 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . . 36 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . . .50 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . 58 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . . 72 SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SIM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Interrupt Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . . 88
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List of Figures
Figure 8-12 8-13 8-14 8-15 8-16 8-17 8-18 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 9-24 9-25 9-26 9-27 9-28 Title Page
Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . .90 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Wait Recovery from Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . . 92 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Stop Mode Recovery from Interrupt . . . . . . . . . . . . . . . . . . . . . 93 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 94 USB I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .98 USB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Supported Transaction Types Per Endpoint. . . . . . . . . . . . . . 103 Supported USB Packet Types . . . . . . . . . . . . . . . . . . . . . . . . 104 Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 SOP, Sync Signaling, and Voltage Levels . . . . . . . . . . . . . . . 105 EOP Transaction Voltage Levels . . . . . . . . . . . . . . . . . . . . . . 107 EOP Width Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 External Low-Speed Device Configuration . . . . . . . . . . . . . . .110 Regulator Electrical Connections . . . . . . . . . . . . . . . . . . . . . . 111 Receiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 Differential Input Sensitivity Range. . . . . . . . . . . . . . . . . . . . . 113 Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . 114 USB Address Register (UADDR) . . . . . . . . . . . . . . . . . . . . . . 116 USB Interrupt Register 0 (UIR0) . . . . . . . . . . . . . . . . . . . . . . . 117 USB Interrupt Register 1 (UIR1) . . . . . . . . . . . . . . . . . . . . . . . 118 USB Interrupt Register 2 (UIR2) . . . . . . . . . . . . . . . . . . . . . . . 121 USB Control Register 0 (UCR0) . . . . . . . . . . . . . . . . . . . . . . . 122 USB Control Register 1 (UCR1) . . . . . . . . . . . . . . . . . . . . . . . 123 USB Control Register 2 (UCR2) . . . . . . . . . . . . . . . . . . . . . . . 124 USB Control Register 3 (UCR3) . . . . . . . . . . . . . . . . . . . . . . . 126 USB Control Register 4 (UCR4) . . . . . . . . . . . . . . . . . . . . . . . 128 USB Status Register 0 (USR0). . . . . . . . . . . . . . . . . . . . . . . . 129 USB Status Register 2 (USR1). . . . . . . . . . . . . . . . . . . . . . . . 130 USB Endpoint 0 Data Register (UE0D0-UE0D7). . . . . . . . . . 131 USB Endpoint 1 Data Register (UE1D0-UE1D7). . . . . . . . . . 132 USB Endpoint 2 Data Register (UE2D0-UE2D7). . . . . . . . . . 133
Technical Data 18 List of Figures
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List of Figures
Figure 9-29 9-30 9-31 9-32
Title
Page
OUT Token Data Flow for Receive Endpoint 0. . . . . . . . . . . . 135 SETUP Token Data Flow for Receive Endpoint 0 . . . . . . . . . 136 IN Token Data Flow for Transmit Endpoint 0 . . . . . . . . . . . . . 137 IN Token Data Flow for Transmit Endpoint 1 . . . . . . . . . . . . . 138
10-1 TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10-2 TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 10-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 148 10-4 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . 154 10-5 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . . . 156 10-6 TIM Counter Modulo Registers (TMODH:TMODL). . . . . . . . . 157 10-7 TIM Channel Status and Control Registers (TSC0:TSC1) . . . 158 10-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 10-9 TIM Channel Registers (TCH0H/L:TCH1H/L). . . . . . . . . . . . . 162 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 12-1 12-2 12-3 12-4 13-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .166 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . 167 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .168 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . . 169 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .171 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . . 171 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .173 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . 175 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Port Option Control Register (POCR). . . . . . . . . . . . . . . . . . . 177 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .181 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 181 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . . 184 IRQ Option Control Register (IOCR) . . . . . . . . . . . . . . . . . . .185 Keyboard Module Block Diagram . . . . . . . . . . . . . . . . . . . . . .189
MC68HC08JB1 -- Rev. 2.0 MOTOROLA List of Figures
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List of Figures
Figure 13-2 13-3 14-1 14-2 14-3 15-1 15-2 17-1 17-2 Title Page
Keyboard Status and Control Register (KBSCR) . . . . . . . . . . 194 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . . 195 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . .200 COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . .201 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . .204 20-Pin PDIP (Case #738) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 20-Pin SOIC (Case #751D) . . . . . . . . . . . . . . . . . . . . . . . . . .214
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List of Tables
Table 1-1 2-1 6-1 6-2 8-1 8-2 8-3 8-4 9-1 9-2 10-1 10-2 10-3 11-1 11-2 11-3 11-4 11-5 13-1 13-2 Title Page
Summary of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SIM Module Signal Name Conventions . . . . . . . . . . . . . . . . . . 77 PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Registers not Affected by Normal Reset. . . . . . . . . . . . . . . . . . 84 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 USB Module Pin Name Conventions . . . . . . . . . . . . . . . . . . . .98 Supported Packet Identifiers. . . . . . . . . . . . . . . . . . . . . . . . . . 105 TIM Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . .142 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . .160 Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . . 165 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Port E Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 KBI Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . .188 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
MC68HC08JB1 -- Rev. 2.0 MOTOROLA List of Tables
Technical Data 21
List of Tables
Technical Data 22 List of Tables
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Technical Data -- MC68HC08JB1
Section 1. General Description
1.1 Contents
1.2 1.3 1.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.1 Power Supply Pins (VDD, VSS) . . . . . . . . . . . . . . . . . . . . . . .27 1.5.2 Voltage Regulator Out (VREG) . . . . . . . . . . . . . . . . . . . . . . . 28 1.5.3 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . 29 1.5.4 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.5 External Interrupt Pins (IRQ, PTE4/D-) . . . . . . . . . . . . . . . .29 1.5.6 Port A Input/Output (I/O) Pins (PTA7/KBA7-PTA0/KBA0). .29 1.5.7 Port C I/O Pins (PTC0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5.8 Port D I/O Pins (PTD0/1) . . . . . . . . . . . . . . . . . . . . . . . . . . .30 1.5.9 Port E I/O Pins (PTE4/D-, PTE3/D+, PTE1/TCH0) . . . . . . . 30
1.2 Introduction
The MC68HC08JB1 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA General Description
Technical Data 23
General Description 1.3 Features
Features of the MC68HC08JB1 include: * * * * * * * High-performance M68HC08 architecture Fully upward-compatible object code with M6805, M146805, and M68HC05 Families 3-MHz internal bus frequency 5,632 bytes of on-chip read-only memory (ROM) 128 bytes of on-chip random-access memory (RAM) ROM data security1 13 general-purpose 3.3V input/output (I/O) pins, including: - 8 keyboard interrupts on port A - 50mA sink capability for infrared LED on PTD0/1 pin - 10mA sink capability for PS/2 connection on 2 pins (with USB module disabled) * * 16-bit, 2-channel timer interface module (TIM) with selectable input capture, output compare, PWM capability on one channel Full Universal Serial Bus Specification 1.1 low-speed functions: - 1.5 Mbps data rate - On-chip 3.3V regulator - Endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer - Endpoint 1 with 8-byte transmit buffer - Endpoint 2 with 8-byte transmit buffer * System protection features: - Optional computer operating properly (COP) reset - Optional low-voltage detection with reset - Illegal opcode detection with reset - Illegal address detection with reset
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the ROM difficult for unauthorized users.
Technical Data 24 General Description
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
General Description MCU Block Diagram
* * * *
Low-power design (fully static with stop and wait modes) Master reset pin with internal pull-up and power-on reset External asynchronous interrupt pin with internal pull-up (IRQ) 20-pin plastic dual-in-line package (DIP), or 20-pin small outline integrated circuit package (SOIC)
Features of the CPU08 include the following: * * * * * * * * * * Enhanced HC05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer Memory-to-memory data transfers Fast 8 x 8 multiply instruction Fast 16/8 divide instruction Binary-coded decimal (bcd) instructions Optimization for controller applications Efficient C language support
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC08JB1.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA General Description
Technical Data 25
Technical Data
(1), (2) (1), (3)
General Description
DDRA
PTA
DDRC
PTC
DDRD
PTD
COMPUTER OPERATING PROPERLY MODULE
DDRE
PTE
USB MODULE VDD POWER VSS USB ENDPOINT 0, 1, 2
VREG 3.3 V
INTERNAL VOLTAGE REGULATOR
(1) Pins have 5V logic. (2) Pin has integrated pullup device. (3) Pins have software configurable pullup device. (4) Pin is open-drain when configured as output. (5) Pins have 10mA sink capability. (6) Pin has 50mA sink capability.
Figure 1-1. MCU Block Diagram
LS USB TRANSCEIVER
26 General Description MOTOROLA
INTERNAL BUS M68HC08 CPU CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU) KEYBOARD INTERRUPT MODULE CONTROL AND STATUS REGISTERS -- 64 BYTES TIMER INTERFACE MODULE USER ROM -- 5,632 BYTES PTC0 (3)
PTA7/KBA7 (3) : PTA0/KBA0 (3)
USER RAM -- 128 BYTES
MONITOR ROM -- 464 BYTES LOW VOLTAGE INHIBIT MODULE PTD0/1(4) (6)
USER VECTORS -- 16 BYTES OSC1 OSC2
OSCILLATOR
POWER-ON RESET MODULE PTE4/D- (3) (4) (5) PTE3/D+ (3) (4) (5) PTE1/TCH0 (3)
RST
SYSTEM INTEGRATION MODULE IRQ MODULE
IRQ
MC68HC08JB1 -- Rev. 2.0
General Description Pin Assignments
1.5 Pin Assignments
VSS OSC1 OSC2 VREG VDD PTD0/1 PTE1/TCH0 PTE3/D+ PTE4/D- PTC0
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
RST PTA0/KBA0 PTA1/KBA1 PTA2/KBA2 PTA3/KBA3 PTA4/KBA4 PTA5/KBA5 PTA6/KBA6 PTA7/KBA7 IRQ
Figure 1-2. 20-pin PDIP/SOIC Pin Assignments
NOTE:
The PTD0 and PTD1 internal pads are bonded together to PTD0/1 pin.
1.5.1 Power Supply Pins (VDD, VSS) VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-3 shows. Place the bypass capacitors as close to the MCU power pins as possible. Use high-frequency-response ceramic capacitors for CBYPASS. CBULK are optional bulk current bypass capacitors for use in applications that require the port pins to source high current levels.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA General Description
Technical Data 27
General Description
MCU
VDD VSS
CBYPASS 0.1 F + CBULK
VDD NOTE: Values shown are typical values.
Figure 1-3. Power Supply Bypassing
1.5.2 Voltage Regulator Out (VREG) VREG is the 3.3 V output of the on-chip voltage regulator. VREG is used internally for the MCU operation and the USB data driver. It is also used to supply the voltage for the external pullup resistor required on the USB's D- line. The VREG pin requires an external bulk capacitor 4.7F or larger and a 0.1 F ceramic bypass capacitor as Figure 1-4 shows. Place the bypass capacitors as close to the VREG pin as possible.
VREG
MCU
VSS
CREGBYPASS 0.1 F + CREGBULK > 4.7 F VREG
Figure 1-4. Regulator Supply Capacitor Configuration
Technical Data 28 General Description
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
General Description Pin Assignments
1.5.3 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit.
1.5.4 External Reset Pin (RST) A logic zero on the RST pin forces the MCU to a known start-up state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. The RST pin contains an internal pullup device to VDD. (See Section 8. System Integration Module (SIM).)
1.5.5 External Interrupt Pins (IRQ, PTE4/D-) IRQ is an asynchronous external interrupt pin. IRQ is also the pin to enter monitor mode. The IRQ pin contains a software configurable pullup device to VDD. PTE4/D- can be programmed to trigger the IRQ interrupt. (See Section 12. External Interrupt (IRQ).)
1.5.6 Port A Input/Output (I/O) Pins (PTA7/KBA7-PTA0/KBA0) PTA7/KBA7-PTA0/KBA0 are general-purpose bidirectional I/O port pins. (See Section 11. Input/Output Ports (I/O).) Each pin contains a software configurable pullup device to VREG when the pin is configured as an input. (See 11.7 Port Options.) Each pin can also be programmed as an external keyboard interrupt pins. (See Section 13. Keyboard Interrupt Module (KBI).)
1.5.7 Port C I/O Pins (PTC0) PTC0 is a general-purpose bidirectional I/O port pin. (See Section 11. Input/Output Ports (I/O).) This pin contains a software configurable pullup device to VREG when the pin is configured as an input. (See 11.7 Port Options.)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA General Description
Technical Data 29
General Description
1.5.8 Port D I/O Pins (PTD0/1) PTD0/1 is a general-purpose bidirectional I/O port pin; open-drain when configured as an output. (See Section 11. Input/Output Ports (I/O).) This pin is software configurable to be a 50mA infrared LED sink port pin. (See 11.7 Port Options.) 1.5.9 Port E I/O Pins (PTE4/D-, PTE3/D+, PTE1/TCH0) Port E is a 3-bit special function port that shares two of its pins with the USB module and one of its pins with the timer interface module. PTE1 pin contains a software configurable pullup device to VREG when the pin is configured as an input or output. When the USB module is disabled, the PTE4 and PTE3 pins are general-purpose bidirectional I/O port pins with 10mA sink capability. Each pin is open-drain when configured as an output; and each pin contains a software configurable 5k pullup to VDD when configured as an input. The PTE4 pin can also be enabled to trigger the IRQ interrupt. When the USB module is enabled, the PTE4/D- and PTE3/D+ pins become the USB module D- and D+ pins. The D- pin contains a software configurable 1.5k pullup to VREG. (See Section 10. Timer Interface Module (TIM), Section 9. Universal Serial Bus Module (USB) and Section 11. Input/Output Ports (I/O).) Summary of the pin functions are provided in Table 1-1.
Technical Data 30 General Description
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
General Description Pin Assignments
Table 1-1. Summary of Pin Functions
PIN NAME VDD VSS VREG RST Power supply. Power supply ground. 3.3V regulated output from MCU. Reset input; active low. With internal pullup to VDD and schmitt trigger input. External IRQ pin; with programmable internal pullup to VDD and schmitt trigger input. Used for mode entry selection. OSC1 OSC2 PTA0/KBA0 : PTA7/KBA7 Crystal oscillator input. Crystal oscillator output; inverting of OSC1 signal. 8-bit general-purpose I/O port. Pins as keyboard interrupts, KBA0-KBA7. Each pin has programmable internal pullup to VREG when configured as input. General-purpose I/O pin. PTC0 Pin has programmable internal pullup to VREG when configured as input. General-purpose I/O pin; open-drain when configured as output. Pin has configurable 50mA sink for infrared LED. General-purpose I/O pin. PTE1/TCH0 Pin has programmable internal pullup to VREG when configured as input or output. Pin as TCH0 of timer interface module. PTE3-PTE4 are general-purpose I/O pins; open-drain when configured as output. PTE3/D+ PTE4/D- PTE3-PTE4 have programmable internal pullup to VDD when configured as input. Pin as D+ of USB module. Pin as D- of USB module. Pin as additional IRQ interrupt. PIN DESCRIPTION IN/OUT IN OUT OUT IN/OUT IN IN IN OUT IN/OUT IN IN IN/OUT IN IN OUT OUT IN/OUT IN/OUT IN/OUT IN OUT IN IN/OUT IN/OUT IN VOLTAGE LEVEL 4.0 to 5.5V 0V VREG (3.3V) VDD VDD VREG to VDD +VHI VREG VREG VREG VREG VREG VREG VREG VREG VREG or VDD VREG or VDD VREG VREG VREG VDD VREG or VDD VDD VREG VREG VDD
IRQ
PTD0/1
MC68HC08JB1 -- Rev. 2.0 MOTOROLA General Description
Technical Data 31
General Description
Technical Data 32 General Description
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Technical Data -- MC68HC08JB1
Section 2. Memory Map
2.1 Contents
2.2 2.3 2.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2 Introduction
The CPU08 can address 64-Kbytes of memory space. The memory map, shown in Figure 2-1, includes: * * * * 5,632 bytes of user ROM 128 bytes of RAM 16 bytes of user-defined vectors 464 bytes of monitor ROM
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Memory Map
Technical Data 33
Memory Map
$0000 $003F $0040 $007F $0080 $00FF $0100 $E5FF $E600 $FBFF $FC00 $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE0F $FE10 $FFDF $FFE0 $FFEF $FFF0 $FFFF
I/O Registers 64 Bytes Unimplemented 64 Bytes RAM 128 Bytes Unimplemented 58,624 Bytes User ROM 5,632 Bytes Reserved 512 Bytes Reserved Reset Status Register (RSR) Reserved Reserved Interrupt Status Register 1 (INT1) Reserved Reserved
Monitor ROM 464 Bytes Reserved 16 Bytes User ROM Vectors 16 Bytes
Figure 2-1. Memory Map
Technical Data 34 Memory Map
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Memory Map I/O Section
2.3 I/O Section
Addresses $0000-$003F, shown in Figure 2-2, contain most of the control, status, and data registers. Additional I/O registers have these addresses: * * * * * * * * $FE00; reserved $FE01; reset status register, RSR $FE02; reserved $FE03; reserved $FE04; interrupt status register 1, INT1 $FE05; reserved $FE06 to $FE0F; reserved $FFFF; COP control register, COPCTL
2.4 Monitor ROM
The 464 bytes at addresses $FE10-$FFDF are reserved ROM addresses that contain the instructions for the monitor functions.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Memory Map
Technical Data 35
Memory Map
Addr.
Register Name Read: Port A Data Register Write: (PTA) Reset: Read:
Bit 7 PTA7
6 PTA6
5 PTA5
4 PTA4
3 PTA3
2 PTA2
1 PTA1
Bit 0 PTA0
$0000
Unaffected by reset
$0001
Unimplemented Write: Reset: Read: Port C Data Register Write: (PTC) Reset: Read: Port D Data Register Write: (PTD) Reset: 0 0 0 0 0 0 0 PTC0
$0002
Unaffected by reset 0 0 0 0 0 0 PTD1 PTD0
$0003
Unaffected by reset DDRA6 0 DDRA5 0 DDRA4 0 DDRA3 0 DDRA2 0 DDRA1 0 DDRA0 0
Read: DDRA7 Data Direction Register A $0004 Write: (DDRA) Reset: 0* * DDRA7 bit is reset by POR or LVI reset only. Read: $0005 Unimplemented Write: Reset: Read: Data Direction Register C $0006 Write: (DDRC) Reset: Read: Data Direction Register D $0007 Write: (DDRD) Reset: Read: Port E Data Register Write: (PTE) Reset: 0
0
0
0
0
0
0
DDRC0 0 DDRD0 0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 DDRD1 0 PTE1
0 0
0 0
0 0
0 PTE4
0 PTE3
0 0
$0008
Unaffected by reset 0 0 0 DDRE4 0 R DDRE3 0 = Reserved 0 DDRE1 0 0
Read: Data Direction Register E $0009 Write: (DDRE) Reset:
0
0
0
0
0
= Unimplemented
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8)
Technical Data 36 Memory Map MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Memory Map Monitor ROM
Addr.
Register Name Read: TIM Status and Control Register Write: (TSC) Reset: Read:
Bit 7 TOF 0 0
6 TOIE 0
5 TSTOP 1
4 0 TRST 0
3 0
2 PS2 0
1 PS1 0
Bit 0 PS0 0
$000A
0
$000B
Unimplemented Write:
$000C
Read: TIM Counter Register High Write: (TCNTH) Reset: Read: TIM Counter Register Low Write: (TCNTL) Reset: Read: TIM Counter Modulo Register High Write: (TMODH) Reset: Read: TIM Counter Modulo Register Low Write: (TMODL) Reset:
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
0 Bit7
0 Bit6
0 Bit5
0 Bit4
0 Bit3
0 Bit2
0 Bit1
0 Bit0
$000D
0 Bit15 1 Bit7 1 CH0F 0 0 Bit15
0 Bit14 1 Bit6 1 CH0IE 0 Bit14
0 Bit13 1 Bit5 1 MS0B 0 Bit13
0 Bit12 1 Bit4 1 MS0A 0 Bit12
0 Bit11 1 Bit3 1 ELS0B 0 Bit11
0 Bit10 1 Bit2 1 ELS0A 0 Bit10
0 Bit9 1 Bit1 1 TOV0 0 Bit9
0 Bit8 1 Bit0 1 CH0MAX 0 Bit8
$000E
$000F
Read: TIM Channel 0 Status and $0010 Control Register Write: (TSC0) Reset: Read: TIM Channel 0 Register High Write: (TCH0H) Reset: Read: TIM Channel 0 Register Low Write: (TCH0L) Reset:
$0011
Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
$0012
Indeterminate after reset CH1F 0 0 CH1IE 0 0 MS1A 0 R ELS1B 0 = Reserved ELS1A 0 TOV1 0 CH1MAX 0
Read: TIM Channel 1 Status and $0013 Control Register Write: (TSC1) Reset:
0
= Unimplemented
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 8)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Memory Map
Technical Data 37
Memory Map
Addr.
Register Name Read: TIM Channel 1 Register High Write: (TCH1H) Reset: Read: TIM Channel 1 Register Low Write: (TCH1L) Reset: Read: Keyboard Status and Control Register Write: (KBSCR) Reset: Read: Keyboard Interrupt Enable Register Write: (KBIER) Reset:
Bit 7 Bit15
6 Bit14
5 Bit13
4 Bit12
3 Bit11
2 Bit10
1 Bit9
Bit 0 Bit8
$0014
Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
$0015
Indeterminate after reset 0 0 0 0 KEYF 0 ACKK 0 KBIE7 0 0 KBIE6 0 0 RSTFR 0 STALL2 0 0 TX1STR 0 0 0 KBIE5 0 0 TXD2FR 0 TX2E 0 0 0 0 KBIE4 0 0 0 KBIE3 0 0 0 KBIE2 0 0 IMASKK 0 KBIE1 0 0 MODEK 0 KBIE0 0 0 RXD0FR 0 TP2SIZ0 0
$0016
$0017
$0018
Read: 0 USB Interrupt Register 2 Write: EOPFR (UIR2) Reset: 0 Read: USB Control Register 2 Write: (UCR2) Reset: Read: USB Control Register 3 Write: (UCR3) Reset: T2SEQ 0 TX1ST
TDX1FR RESUMFR TXD0FR 0 TP2SIZ3 0 0 0 TP2SIZ2 0 0 TP2SIZ1 0
$0019
0
$001A
OSTALL0 ISTALL0 0 0
PULLEN ENABLE2 ENABLE1 0* 0 0
0
* PULLEN bit is reset by POR or LVI reset only. Read: USB Control Register 4 Write: (UCR4) Reset: Read: IRQ Option Control Register Write: (IOCR) Reset: 0 0 0 0 0 FUSBO 0 PTE4IF FDP 0 PTE4IE 0 0 FDM 0 IRQPD 0 PAP 0
$001B
0 0
0 0
0 0
0 0
0 0
$001C
0
0 0
0 PTDILDD 0
0 PTE4P 0 R
0 PTE3P 0 = Reserved
0 PCP 0
$001D
Read: Port Option Control PTE20P Register Write: (POCR) Reset: 0
0
0
= Unimplemented
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 8)
Technical Data 38 Memory Map MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Memory Map Monitor ROM
Addr.
Register Name Read: IRQ Status and Control Register Write: (ISCR) Reset: Read: Configuration Register Write: (CONFIG) Reset:
Bit 7 0
6 0
5 0
4 0
3 IRQF
2 0 ACK
1 IMASK 0 STOP 0
Bit 0 MODE 0 COPD 0
$001E
0 0
0 0
0 URSTD 0
0 LVID 0
0 SSREC 0
0 COPRS 0
$001F
0
0
One-time writable register after each reset. URSTD and LVID bits are reset by POR or LVI reset only. Read: UE0R07 USB Endpoint 0 Data Register 0 Write: UE0T07 (UE0D0) Reset: Read: UE0R17 USB Endpoint 0 Data Register 1 Write: UE0T17 (UE0D1) Reset: Read: UE0R27 USB Endpoint 0 Data Register 2 Write: UE0T27 (UE0D2) Reset: Read: UE0R37 USB Endpoint 0 Data Register 3 Write: UE0T37 (UE0D3) Reset: Read: UE0R47 USB Endpoint 0 Data Register 4 Write: UE0T47 (UE0D4) Reset: Read: UE0R57 USB Endpoint 0 Data Register 5 Write: UE0T57 (UE0D5) Reset: Read: UE0R67 USB Endpoint 0 Data Register 6 Write: UE0T67 (UE0D6) Reset: Read: UE0R77 USB Endpoint 0 Data Register 7 Write: UE0T77 (UE0D7) Reset: UE0R06 UE0T06 UE0R05 UE0T05 UE0R04 UE0T04 UE0R03 UE0T03 UE0R02 UE0T02 UE0R01 UE0T01 UE0R00 UE0T00
$0020
Unaffected by reset UE0R16 UE0T16 UE0R15 UE0T15 UE0R14 UE0T14 UE0R13 UE0T13 UE0R12 UE0T12 UE0R11 UE0T11 UE0R10 UE0T10
$0021
Unaffected by reset UE0R26 UE0T26 UE0R25 UE0T25 UE0R24 UE0T24 UE0R23 UE0T23 UE0R22 UE0T22 UE0R21 UE0T21 UE0R20 UE0T20
$0022
Unaffected by reset UE0R36 UE0T36 UE0R35 UE0T35 UE0R34 UE0T34 UE0R33 UE0T33 UE0R32 UE0T32 UE0R31 UE0T31 UE0R30 UE0T30
$0023
Unaffected by reset UE0R46 UE0T46 UE0R45 UE0T45 UE0R44 UE0T44 UE0R43 UE0T43 UE0R42 UE0T42 UE0R41 UE0T41 UE0R40 UE0T40
$0024
Unaffected by reset UE0R56 UE0T56 UE0R55 UE0T55 UE0R54 UE0T54 UE0R53 UE0T53 UE0R52 UE0T52 UE0R51 UE0T51 UE0R50 UE0T50
$0025
Unaffected by reset UE0R66 UE0T66 UE0R65 UE0T65 UE0R64 UE0T64 UE0R63 UE0T63 UE0R62 UE0T62 UE0R61 UE0T61 UE0R60 UE0T60
$0026
Unaffected by reset UE0R76 UE0T76 UE0R75 UE0T75 UE0R74 UE0T74 UE0R73 UE0T73 UE0R72 UE0T72 UE0R71 UE0T71 UE0R70 UE0T70
$0027
Unaffected by reset = Unimplemented R = Reserved U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Memory Map Technical Data 39
Memory Map
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0028
Read: USB Endpoint 1 Data Register 0 Write: UE1T07 (UE1D0) Reset: Read: USB Endpoint 1 Data Register 1 Write: UE1T17 (UE1D1) Reset: Read: USB Endpoint 1 Data Register 2 Write: UE1T27 (UE1D2) Reset: Read: USB Endpoint 1 Data Register 3 Write: UE1T37 (UE1D3) Reset: Read: USB Endpoint 1 Data Register 4 Write: UE1T47 (UE1D4) Reset: Read: USB Endpoint 1 Data Register 5 Write: UE1T57 (UE1D5) Reset: Read: USB Endpoint 1 Data Register 6 Write: UE1T67 (UE1D6) Reset: Read: USB Endpoint 1 Data Register 7 Write: UE1T77 (UE1D7) Reset: Read: USB Endpoint 2 Data Register 0 Write: UE2T07 (UE2D0) Reset: Read: USB Endpoint 2 Data Register 1 Write: UE2T17 (UE2D1) Reset:
UE1T06
UE1T05
UE1T04
UE1T03
UE1T02
UE1T01
UE1T00
Unaffected by reset
$0029
UE1T16
UE1T15
UE1T14
UE1T13
UE1T12
UE1T11
UE1T10
Unaffected by reset
$002A
UE1T26
UE1T25
UE1T24
UE1T23
UE1T22
UE1T21
UE1T20
Unaffected by reset
$002B
UE1T36
UE1T35
UE1T34
UE1T33
UE1T32
UE1T31
UE1T30
Unaffected by reset
$002C
UE1T46
UE1T45
UE1T44
UE1T43
UE1T42
UE1T41
UE1T40
Unaffected by reset
$002D
UE1T56
UE1T55
UE1T54
UE1T53
UE1T52
UE1T51
UE1T50
Unaffected by reset
$002E
UE1T66
UE1T65
UE1T64
UE1T63
UE1T62
UE1T61
UE1T60
Unaffected by reset
$002F
UE1T76
UE1T75
UE1T74
UE1T73
UE1T72
UE1T71
UE1T70
Unaffected by reset
$0030
UE2T06
UE2T05
UE2T04
UE2T03
UE2T02
UE2T01
UE2T00
Unaffected by reset
$0031
UE2T16
UE2T15
UE2T14
UE2T13
UE2T12
UE2T11
UE2T10
Unaffected by reset = Unimplemented R = Reserved U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 8)
Technical Data 40 Memory Map
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Memory Map Monitor ROM
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0032
Read: USB Endpoint 2 Data Register 2 Write: UE2T27 (UE2D2) Reset: Read: USB Endpoint 2 Data Register 3 Write: UE2T37 (UE2D3) Reset: Read: USB Endpoint 2 Data Register 4 Write: UE2T47 (UE2D4) Reset: Read: USB Endpoint 2 Data Register 5 Write: UE2T57 (UE2D5) Reset: Read: USB Endpoint 2 Data Register 6 Write: UE2T67 (UE2D6) Reset: Read: USB Endpoint 2 Data Register 7 Write: UE2T77 (UE2D7) Reset: Read: USBEN USB Address Register Write: (UADDR) Reset: 0*
UE2T26
UE2T25
UE2T24
UE2T23
UE2T22
UE2T21
UE2T20
Unaffected by reset
$0033
UE2T36
UE2T35
UE2T34
UE2T33
UE2T32
UE2T31
UE2T30
Unaffected by reset
$0034
UE2T46
UE2T45
UE2T44
UE2T43
UE2T42
UE2T41
UE2T40
Unaffected by reset
$0035
UE2T56
UE2T55
UE2T54
UE2T53
UE2T52
UE2T51
UE2T50
Unaffected by reset
$0036
UE2T66
UE2T65
UE2T64
UE2T63
UE2T62
UE2T61
UE2T60
Unaffected by reset
$0037
UE2T76
UE2T75
UE2T74
UE2T73
UE2T72
UE2T71
UE2T70
Unaffected by reset UADD6 0 UADD5 0 UADD4 0 UADD3 0 UADD2 0 UADD1 0 UADD0 0
$0038
* USBEN bit is reset by POR or LVI reset only. Read: USB Interrupt Register 0 Write: (UIR0) Reset: Read: USB Interrupt Register 1 Write: (UIR1) Reset: Read: USB Control Register 0 Write: (UCR0) Reset: EOPIE 0 EOPF SUSPND 0 RSTF TXD2IE 0 TXD2F 0 TXD1IE 0 TXD1F 0 TXD0IE 0 TXD0F RXD0IE 0 RXD0F
$0039
0 0
0 RESUMF
$003A
0 T0SEQ 0
0 0
0 TX0E 0
0 RX0E 0 R
0 TP0SIZ3 0 = Reserved
0 TP0SIZ2 0
0 TP0SIZ1 0
0 TP0SIZ0 0
$003B
0
= Unimplemented
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 8)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Memory Map Technical Data 41
Memory Map
Addr.
Register Name Read: USB Control Register 1 Write: (UCR1) Reset:
Bit 7 T1SEQ 0
6 STALL1 0 SETUP
5 TX1E 0 0
4
3
2 TP1SIZ2 0 RP0SIZ2
1 TP1SIZ1 0 RP0SIZ1
Bit 0 TP1SIZ0 0 RP0SIZ0
$003C
FRESUM TP1SIZ3 0 0 0 RP0SIZ3
$003D
Read: R0SEQ USB Status Register 0 Write: (USR0) Reset: Read: USB Status Register 1 Write: (USR1) Reset: Read: 0
Unaffected by reset TXACK TXNAK TXSTL 0 0 0 0
$003E
0
0
0
0
0
0
0
0
$003F
Unimplemented Write:
Read: $FE00 Reserved Write:
R
R
R
R
R
R
R
R
$FE01
Read: Reset Status Register Write: (RSR) POR: Read:
POR
PIN
COP
ILOP
ILAD
USB
LVI
0
1 R
0 R
0 R
0 R
0 R
0 R
0 R
0 R
$FE02
Reserved Write:
Read: $FE03 Reserved Write:
R
R
R
R
R
R
R
R
Read: Interrupt Status Register 1 $FE04 Write: (INT1) Reset: Read: $FE05 Reserved Write:
IF6 R 0 R
IF5 R 0 R
IF4 R 0 R
IF3 R 0 R
IF2 R 0 R
IF1 R 0 R
0 R 0 R
0 R 0 R
= Unimplemented
R
= Reserved
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 8)
Technical Data 42 Memory Map
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Memory Map Monitor ROM
Addr. $FE06 $FE0F
Register Name Read: Reserved Write:
Bit 7 R
6 R
5 R
4 R
3 R
2 R
1 R
Bit 0 R
$FFFF
Read: COP Control Register Write: (COPCTL) Reset:
Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset = Unimplemented R = Reserved U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 8) Table 2-1 is a list of vector locations. Table 2-1. Vector Addresses
Vector Priority Lowest IF6 $FFF1 $FFF2 IF5 $FFF3 $FFF4 IF4 $FFF5 $FFF6 IF3 $FFF7 $FFF8 IF1 $FFF9 $FFFA IF2 $FFFB $FFFC -- $FFFD $FFFE -- Highest $FFFF Reset Vector (Low) SWI Vector (Low) Reset Vector (High) USB Vector (Low) SWI Vector (High) IRQ Vector (Low) USB Vector (High) TIM Channel 0 Vector (Low) IRQ Vector (High) TIM Channel 1 Vector (Low) TIM Channel 0 Vector (High) TIM Overflow Vector (Low) TIM Channel 1 Vector (High) Keyboard Vector (Low) TIM Overflow Vector (High) Vector Address $FFF0 Vector Keyboard Vector (High)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Memory Map
Technical Data 43
Memory Map
Technical Data 44 Memory Map
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Technical Data -- MC68HC08JB1
Section 3. Random-Access Memory (RAM)
3.1 Contents
3.2 3.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2 Introduction
This section describes the 128 bytes of RAM.
3.3 Functional Description
Addresses $0080-$00FF are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.
NOTE:
For correct operation, the stack pointer must point only to RAM locations. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers.
NOTE:
For M6805 Family compatibility, the H register is not stacked. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls.
NOTE:
Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Random-Access Memory (RAM)
Technical Data 45
Random-Access Memory (RAM)
Technical Data 46 Random-Access Memory (RAM)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Technical Data -- MC68HC08JB1
Section 4. Read-Only Memory (ROM)
4.1 Contents
4.2 4.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2 Introduction
This section describes the 5,632 bytes of ROM (read-only memory).
4.3 Functional Description
These addresses are user ROM locations: $E600-$FBFF (user memory; 5,632 bytes) $FFF0-$FFFF (user vectors; 16 bytes)
NOTE:
A security feature prevents viewing of the ROM contents.1
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the ROM contents difficult for unauthorized users.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Read-Only Memory (ROM)
Technical Data 47
Read-Only Memory (ROM)
Technical Data 48 Read-Only Memory (ROM)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Technical Data -- MC68HC08JB1
Section 5. Configuration Register (CONFIG)
5.1 Contents
5.2 5.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.2 Introduction
This section describes the configuration register (CONFIG). This writeonce-after-reset register controls the following options: * * * * * * USB reset Low voltage inhibit Stop mode recovery time (2048 or 4096 OSCXCLK cycles) COP timeout period (218 - 24 or 213 - 24 OSCXCLK cycles) STOP instruction Computer operating properly module (COP)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Configuration Register (CONFIG)
Technical Data 49
Configuration Register (CONFIG) 5.3 Functional Description
The configuration register is used in the initialization of various options. The configuration register can be written once after each reset. Bit-5 and bit-4 are cleared by a POR or LVI reset only. Bit-3 to bit-0 are cleared during any reset. Since the various options affect the operation of the MCU, it is recommended that this register be written immediately after reset. The configuration register is located at $001F. The configuration register may be read at any time.
Address: $001F Bit 7 Read: Write: Reset: 0 0 0* 0* 0 0 0 0 0 6 0 URSTD LVID SSREC COPRS STOP COPD 5 4 3 2 1 Bit 0
= Unimplemented
* URSTD and LVID bits are reset by POR or LVI reset only.
Figure 5-1. Configuration Register (CONFIG) URSTD -- USB Reset Disable Bit URSTD disables the USB reset signal generating an internal reset to the CPU and internal registers. Instead, it will generate an interrupt request to the CPU. 1 = USB reset generates a USB interrupt request to CPU 0 = USB reset generates a chip reset LVID -- Low Voltage Inhibit Disable Bit LVID disables the LVI circuit 1 = Disable LVI circuit 0 = Enable LVI circuit SSREC -- Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 2048xOSCXCLK cycles instead of a 4096xOSCXCLK cycle delay. 1 = Stop mode recovery after 2048xOSCXCLK cycles 0 = Stop mode recovery after 4096xOSCXCLK cycles
Technical Data 50 Configuration Register (CONFIG)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Configuration Register (CONFIG) Functional Description
NOTE:
Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal, do not set the SSREC bit. COPRS -- COP Rate Select Bit COPD selects the COP timeout period. Reset clears COPRS. (See Section 14. Computer Operating Properly (COP).) 1 = COP timeout period = (213 - 24)xOSCXCLK cycles 0 = COP timeout period = (218 - 24)xOSCXCLK cycles STOP -- STOP Instruction Enable Bit STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD -- COP Disable Bit COPD disables the COP module. (See Section 14. Computer Operating Properly (COP).) 1 = COP module disabled 0 = COP module enabled
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Configuration Register (CONFIG)
Technical Data 51
Configuration Register (CONFIG)
Technical Data 52 Configuration Register (CONFIG)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Technical Data -- MC68HC08JB1
Section 6. Central Processor Unit (CPU)
6.1 Contents
6.2 6.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.4.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 6.4.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.4.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.4.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.4.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .58 6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .60
6.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 6.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6.7 6.8 6.9 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU)
Technical Data 53
Central Processor Unit (CPU) 6.2 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.
6.3 Features
Feature of the CPU include: * * * * * * * * * * * Object code fully upward-compatible with M68HC05 Family 16-bit stack pointer with stack manipulation instructions 16-bit index register with X-register manipulation instructions 3-MHz CPU internal bus frequency 64-Kbyte program/data memory space 16 addressing modes Memory-to-memory data moves without using accumulator Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions Enhanced binary-coded decimal (BCD) data handling Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes Low-power stop and wait modes
Technical Data 54 Central Processor Unit (CPU)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Central Processor Unit (CPU) CPU Registers
6.4 CPU Registers
Figure 6-1 shows the five CPU registers. CPU registers are not part of the memory map.
7 15 H 15 15 X
0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X) 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC)
7 0 V11HINZC
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO'S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
6.4.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
Bit 7
Read: Write: Reset: Unaffected by reset
6
5
4
3
2
1
Bit 0
Figure 6-2. Accumulator (A)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU)
Technical Data 55
Central Processor Unit (CPU)
6.4.2 Index Register The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location.
Bit 15
Read: Write: Reset: 0 0 0 0 0 0 0 0 X X X X X X X X
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit 0
X = Indeterminate
Figure 6-3. Index Register (H:X) 6.4.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand.
Bit 15
Read: Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit 0
Figure 6-4. Stack Pointer (SP)
Technical Data 56 Central Processor Unit (CPU)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Central Processor Unit (CPU) CPU Registers
NOTE:
The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations.
6.4.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit 15
Read: Write: Reset: Loaded with Vector from $FFFE and $FFFF
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit 0
Figure 6-5. Program Counter (PC)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU)
Technical Data 57
Central Processor Unit (CPU)
6.4.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register.
Bit 7
Read: V Write: Reset: X X = Indeterminate 1 1 X 1 X X X 1 1 H I N Z C
6
5
4
3
2
1
Bit 0
Figure 6-6. Condition Code Register (CCR) V -- Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H -- Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or addwith-carry (ADC) operation. The half-carry flag is required for binarycoded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4
Technical Data 58 Central Processor Unit (CPU)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Central Processor Unit (CPU) CPU Registers
I -- Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled
NOTE:
To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). N -- Negative flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result Z -- Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU)
Technical Data 59
Central Processor Unit (CPU)
C -- Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions -- such as bit test and branch, shift, and rotate -- also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7
6.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Motorola document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU.
6.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
6.6.1 Wait Mode The WAIT instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock
*
Technical Data 60 Central Processor Unit (CPU)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Central Processor Unit (CPU) CPU During Break Interrupts
6.6.2 Stop Mode The STOP instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock
*
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
6.7 CPU During Break Interrupts
If the break module is enabled, a break interrupt causes the CPU to execute the software interrupt instruction (SWI) at the completion of the current CPU instruction. The program counter vectors to $FFFC-$FFFD ($FEFC-$FEFD in monitor mode). A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted.
6.8 Instruction Set Summary
Table 6-1 provides a summary of the M68HC08 instruction set.
6.9 Opcode Map
The opcode map is provided in Table 6-2.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU)
Technical Data 61
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 1 of 8)
Cycles 2 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 2 2 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 3 4 4 4 4 4 4 4 4 Source Form ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP AIS #opr AIX #opr AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP BCC rel Operand ii dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff ii ii ii dd hh ll ee ff ff ff ee ff dd ff ff dd ff ff rr dd dd dd dd dd dd dd dd Address Mode Opcode A9 B9 C9 D9 E9 F9 9EE9 9ED9 AB BB CB DB EB FB 9EEB 9EDB A7 AF A4 B4 C4 D4 E4 F4 9EE4 9ED4 38 48 58 68 78 9E68 37 47 57 67 77 9E67 24 11 13 15 17 19 1B 1D 1F Effect on CCR VH INZC
Operation
Description
Add with Carry
A (A) + (M) + (C)
IMM DIR EXT IX2 - IX1 IX SP1 SP2 IMM DIR EXT IX2 - IX1 IX SP1 SP2 - - - - - - IMM - - - - - - IMM IMM DIR EXT IX2 0--- IX1 IX SP1 SP2 DIR INH INH -- IX1 IX SP1 DIR INH INH -- IX1 IX SP1 - - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) ------ DIR (b4) DIR (b5) DIR (b6) DIR (b7)
Add without Carry
A (A) + (M)
Add Immediate Value (Signed) to SP Add Immediate Value (Signed) to H:X
SP (SP) + (16 M) H:X (H:X) + (16 M)
Logical AND
A (A) & (M)
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
Arithmetic Shift Right
b7 b0
C
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? (C) = 0
BCLR n, opr
Clear Bit n in M
Mn 0
Technical Data 62 Central Processor Unit (CPU)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Central Processor Unit (CPU) Opcode Map
Table 6-1. Instruction Set Summary (Sheet 2 of 8)
Cycles 3 3 3 3 3 3 3 3 3 3 2 3 4 4 3 2 4 5 3 3 3 3 3 3 3 3 3 3 Source Form BCS rel BEQ rel BGE opr BGT opr BHCC rel BHCS rel BHI rel BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP BLE opr BLO rel BLS rel BLT opr BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel Operand rr rr rr rr rr rr rr rr rr rr ii dd hh ll ee ff ff ff ee ff rr rr rr rr rr rr rr rr rr rr Address Mode Opcode 25 27 90 92 28 29 22 24 2F 2E A5 B5 C5 D5 E5 F5 9EE5 9ED5 93 25 23 91 2C 2B 2D 26 2A 20 Effect on CCR VH INZC Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Greater Than or Equal To (Signed Operands) Branch if Greater Than (Signed Operands) Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if Higher Branch if Higher or Same (Same as BCC) Branch if IRQ Pin High Branch if IRQ Pin Low PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (Z) = 1 PC (PC) + 2 + rel ? (N V) = 0
PC (PC) + 2 + rel ? (Z) | (N V) = 0
Operation
Description
- - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL IMM DIR EXT IX2 0--- IX1 IX SP1 SP2 - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL
PC (PC) + 2 + rel ? (H) = 0 PC (PC) + 2 + rel ? (H) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 0 PC (PC) + 2 + rel ? (C) = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0
Bit Test
(A) & (M)
Branch if Less Than or Equal To (Signed Operands) Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Less Than (Signed Operands) Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? (Z) | (N V) = 1
PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 1 PC (PC) + 2 + rel ? (N V) =1 PC (PC) + 2 + rel ? (I) = 0 PC (PC) + 2 + rel ? (N) = 1 PC (PC) + 2 + rel ? (I) = 1 PC (PC) + 2 + rel ? (Z) = 0 PC (PC) + 2 + rel ? (N) = 0 PC (PC) + 2 + rel
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU)
Technical Data 63
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 3 of 8)
Cycles 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 5 4 4 5 4 6 1 2 dd 3 1 1 1 3 2 4 Source Form Operand dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd rr dd rr ii rr ii rr ff rr rr ff rr ff ff Address Mode Opcode 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E AD 31 41 51 61 71 9E61 98 9A 3F 4F 5F 8C 6F 7F 9E6F Effect on CCR VH INZC
Operation
Description
BRCLR n,opr,rel Branch if Bit n in M Clear
PC (PC) + 3 + rel ? (Mn) = 0
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ----- DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) ----- DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) ------ DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BRN rel
Branch Never
PC (PC) + 2
BRSET n,opr,rel Branch if Bit n in M Set
PC (PC) + 3 + rel ? (Mn) = 1
BSET n,opr
Set Bit n in M
Mn 1
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel
- - - - - - REL
CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC CLI CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP Clear Carry Bit Clear Interrupt Mask
DIR PC (PC) + 3 + rel ? (A) - (M) = $00 IMM PC (PC) + 3 + rel ? (A) - (M) = $00 IMM PC (PC) + 3 + rel ? (X) - (M) = $00 ------ IX1+ PC (PC) + 3 + rel ? (A) - (M) = $00 IX+ PC (PC) + 2 + rel ? (A) - (M) = $00 SP1 PC (PC) + 4 + rel ? (A) - (M) = $00 C0 I0 M $00 A $00 X $00 H $00 M $00 M $00 M $00 - - - - - 0 INH - - 0 - - - INH DIR INH INH 0 - - 0 1 - INH IX1 IX SP1
Clear
Technical Data 64 Central Processor Unit (CPU)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Central Processor Unit (CPU) Opcode Map
Table 6-1. Instruction Set Summary (Sheet 4 of 8)
Cycles 2 3 4 4 3 2 4 5 4 1 1 4 3 5 3 4 2 3 4 4 3 2 4 5 2 dd rr rr rr ff rr rr ff rr dd 5 3 3 5 4 6 4 1 1 4 3 5 7 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 Source Form CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX COM opr,X COM ,X COM opr,SP CPHX #opr CPHX opr CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP DAA Operand ii dd hh ll ee ff ff ff ee ff dd ff ff ii ii+1 dd ii dd hh ll ee ff ff ff ee ff ff ff Address Mode Opcode A1 B1 C1 D1 E1 F1 9EE1 9ED1 33 43 53 63 73 9E63 65 75 A3 B3 C3 D3 E3 F3 9EE3 9ED3 72 3B 4B 5B 6B 7B 9E6B 3A 4A 5A 6A 7A 9E6A 52 A8 B8 C8 D8 E8 F8 9EE8 9ED8 Effect on CCR VH INZC
Operation
Description
Compare A with M
(A) - (M)
IMM DIR EXT IX2 -- IX1 IX SP1 SP2 DIR INH INH 0--1 IX1 IX SP1 -- IMM DIR
Complement (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (M) X (X) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) (H:X) - (M:M + 1)
Compare H:X with M
Compare X with M
(X) - (M)
IMM DIR EXT IX2 -- IX1 IX SP1 SP2 U - - INH DIR INH - - - - - - INH IX1 IX SP1 DIR INH INH --- IX1 IX SP1 - - - - INH IMM DIR EXT IX2 0--- IX1 IX SP1 SP2
Decimal Adjust A
(A)10
A (A) - 1 or M (M) - 1 or X (X) - 1
DBNZ opr,rel DBNZA rel Decrement and Branch if Not Zero DBNZX rel DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP DIV EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP
PC (PC) + 3 + rel ? (result) 0 PC (PC) + 2 + rel ? (result) 0 PC (PC) + 2 + rel ? (result) 0 PC (PC) + 3 + rel ? (result) 0 PC (PC) + 2 + rel ? (result) 0 PC (PC) + 4 + rel ? (result) 0 M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 M (M) - 1 A (H:A)/(X) H Remainder
Decrement
Divide
Exclusive OR M with A
A (A M)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU)
Technical Data 65
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 5 of 8)
Cycles 4 1 1 4 3 5 2 3 4 3 2 4 5 6 5 4 2 3 4 4 3 2 4 5 3 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 Source Form INC opr INCA INCX INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP LDHX #opr LDHX opr LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP Operand dd ff ff dd hh ll ee ff ff dd hh ll ee ff ff ii dd hh ll ee ff ff ff ee ff ii jj dd ii dd hh ll ee ff ff ff ee ff dd ff ff dd ff ff Address Mode Opcode 3C 4C 5C 6C 7C 9E6C BC CC DC EC FC BD CD DD ED FD A6 B6 C6 D6 E6 F6 9EE6 9ED6 45 55 AE BE CE DE EE FE 9EEE 9EDE 38 48 58 68 78 9E68 34 44 54 64 74 9E64 Effect on CCR VH INZC M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 M (M) + 1
Operation
Description
Increment
DIR INH INH --- IX1 IX SP1 DIR EXT - - - - - - IX2 IX1 IX DIR EXT - - - - - - IX2 IX1 IX IMM DIR EXT IX2 0--- IX1 IX SP1 SP2 0--- IMM DIR
Jump
PC Jump Address
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Unconditional Address
Load A from M
A (M)
Load H:X from M
H:X (M:M + 1)
Load X from M
X (M)
IMM DIR EXT IX2 0--- IX1 IX SP1 SP2 DIR INH INH -- IX1 IX SP1 DIR INH INH --0 IX1 IX SP1
Logical Shift Left (Same as ASL)
C b7 b0
0
Logical Shift Right
0 b7 b0
C
Technical Data 66 Central Processor Unit (CPU)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Central Processor Unit (CPU) Opcode Map
Table 6-1. Instruction Set Summary (Sheet 6 of 8)
Cycles 5 4 4 4 5 dd 4 1 1 4 3 5 1 3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 2 2 2 2 2 2 dd 4 1 1 4 3 5 4 1 1 4 3 5 1 Source Form MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP NOP NSA ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA PSHH PSHX PULA PULH PULX ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP RSP Operand dd dd dd ii dd dd ff ff ff ff dd ff ff Address Mode Opcode 4E 5E 6E 7E 42 30 40 50 60 70 9E60 9D 62 AA BA CA DA EA FA 9EEA 9EDA 87 8B 89 86 8A 88 39 49 59 69 79 9E69 36 46 56 66 76 9E66 9C Effect on CCR VH INZC (M)Destination (M)Source Move H:X (H:X) + 1 (IX+D, DIX+) Unsigned multiply X:A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) None A (A[3:0]:A[7:4])
Operation
Description
DD DIX+ 0--- IMD IX+D - 0 - - - 0 INH DIR INH INH -- IX1 IX SP1 - - - - - - INH - - - - - - INH IMM DIR EXT IX2 0--- IX1 IX SP1 SP2 - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH DIR INH INH -- IX1 IX SP1 DIR INH INH -- IX1 IX SP1 - - - - - - INH
Negate (Two's Complement)
No Operation Nibble Swap A
Inclusive OR A and M
A (A) | (M)
Push A onto Stack Push H onto Stack Push X onto Stack Pull A from Stack Pull H from Stack Pull X from Stack
Push (A); SP (SP) - 1 Push (H); SP (SP) - 1 Push (X); SP (SP) - 1 SP (SP + 1); Pull (A) SP (SP + 1); Pull (H) SP (SP + 1); Pull (X)
Rotate Left through Carry
C b7 b0
Rotate Right through Carry
b7 b0
C
Reset Stack Pointer
SP $FF
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU)
Technical Data 67
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 7 of 8)
Cycles 7 4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 1 2 dd hh ll ee ff ff ff ee ff dd 3 4 4 3 2 4 5 4 1 dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 Source Form Operand Address Mode Opcode 80 81 A2 B2 C2 D2 E2 F2 9EE2 9ED2 99 9B B7 C7 D7 E7 F7 9EE7 9ED7 35 8E BF CF DF EF FF 9EEF 9EDF A0 B0 C0 D0 E0 F0 9EE0 9ED0 Effect on CCR VH INZC SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP SP + 1; Pull (PCH) SP SP + 1; Pull (PCL)
Operation
Description
RTI
Return from Interrupt
INH
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP STHX opr STOP STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP
Return from Subroutine
- - - - - - INH IMM DIR EXT IX2 -- IX1 IX SP1 SP2 - - - - - 1 INH - - 1 - - - INH DIR EXT IX2 0 - - - IX1 IX SP1 SP2 0 - - - DIR - - 0 - - - INH DIR EXT IX2 0 - - - IX1 IX SP1 SP2 IMM DIR EXT IX2 -- IX1 IX SP1 SP2
Subtract with Carry
A (A) - (M) - (C)
Set Carry Bit Set Interrupt Mask
C1 I1
Store A in M
M (A)
Store H:X in M Enable IRQ Pin; Stop Oscillator
(M:M + 1) (H:X) I 0; Stop Oscillator
Store X in M
M (X)
Subtract
A (A) - (M)
Technical Data 68 Central Processor Unit (CPU)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Central Processor Unit (CPU) Opcode Map
Table 6-1. Instruction Set Summary (Sheet 8 of 8)
Cycles 9 2 1 1 dd 3 1 1 3 2 4 2 1 2 Source Form Operand ff ff Address Mode Opcode 83 84 97 85 3D 4D 5D 6D 7D 9E6D 95 9F 94 Effect on CCR VH INZC PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte CCR (A) X (A) A (CCR)
Operation
Description
SWI
Software Interrupt
- - 1 - - - INH
TAP TAX TPA TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP TSX TXA TXS A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N
Transfer A to CCR Transfer A to X Transfer CCR to A
INH - - - - - - INH - - - - - - INH DIR INH INH 0--- IX1 IX SP1 - - - - - - INH - - - - - - INH - - - - - - INH n opr PC PCH PCL REL rel rr SP1 SP2 SP U V X Z & |
Test for Negative or Zero
(A) - $00 or (X) - $00 or (M) - $00
Transfer SP to H:X Transfer X to A Transfer H:X to SP
H:X (SP) + 1 A (X) (SP) (H:X) - 1
Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry bit Index register high byte High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate source to direct destination addressing mode Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, no offset, post increment addressing mode Indexed with post increment to direct addressing mode Indexed, 8-bit offset addressing mode Indexed, 8-bit offset, post increment addressing mode Indexed, 16-bit offset addressing mode Memory location Negative bit
() -( ) #
? : --
Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Central Processor Unit (CPU)
Technical Data 69
Technical Data MC68HC08JB1 -- Rev. 2.0
Central Processor Unit (CPU)
70 Central Processor Unit (CPU) MOTOROLA
Table 6-2. Opcode Map
Bit Manipulation DIR DIR
MSB LSB
Branch REL 2 3 BRA 2 REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL
DIR 3
INH 4
Read-Modify-Write INH IX1 5 1 NEGX 1 INH 4 CBEQX 3 IMM 7 DIV 1 INH 1 COMX 1 INH 1 LSRX 1 INH 4 LDHX 2 DIR 1 RORX 1 INH 1 ASRX 1 INH 1 LSLX 1 INH 1 ROLX 1 INH 1 DECX 1 INH 3 DBNZX 2 INH 1 INCX 1 INH 1 TSTX 1 INH 4 MOV 2 DIX+ 1 CLRX 1 INH 6 4 NEG 2 IX1 5 CBEQ 3 IX1+ 3 NSA 1 INH 4 COM 2 IX1 4 LSR 2 IX1 3 CPHX 3 IMM 4 ROR 2 IX1 4 ASR 2 IX1 4 LSL 2 IX1 4 ROL 2 IX1 4 DEC 2 IX1 5 DBNZ 3 IX1 4 INC 2 IX1 3 TST 2 IX1 4 MOV 3 IMD 3 CLR 2 IX1
SP1 9E6
IX 7
Control INH INH 8 9
IMM A 2 SUB 2 IMM 2 CMP 2 IMM 2 SBC 2 IMM 2 CPX 2 IMM 2 AND 2 IMM 2 BIT 2 IMM 2 LDA 2 IMM 2 AIS 2 IMM 2 EOR 2 IMM 2 ADC 2 IMM 2 ORA 2 IMM 2 ADD 2 IMM
DIR B
EXT C 4 SUB 3 EXT 4 CMP 3 EXT 4 SBC 3 EXT 4 CPX 3 EXT 4 AND 3 EXT 4 BIT 3 EXT 4 LDA 3 EXT 4 STA 3 EXT 4 EOR 3 EXT 4 ADC 3 EXT 4 ORA 3 EXT 4 ADD 3 EXT 3 JMP 3 EXT 5 JSR 3 EXT 4 LDX 3 EXT 4 STX 3 EXT
Register/Memory IX2 SP2 D 4 SUB IX2 4 CMP IX2 4 SBC IX2 4 CPX IX2 4 AND IX2 4 BIT IX2 4 LDA IX2 4 STA IX2 4 EOR IX2 4 ADC IX2 4 ORA IX2 4 ADD IX2 4 JMP IX2 6 JSR IX2 4 LDX IX2 4 STX IX2 9ED 5 SUB SP2 5 CMP SP2 5 SBC SP2 5 CPX SP2 5 AND SP2 5 BIT SP2 5 LDA SP2 5 STA SP2 5 EOR SP2 5 ADC SP2 5 ORA SP2 5 ADD SP2
IX1 E
SP1 9EE 4 SUB 3 SP1 4 CMP 3 SP1 4 SBC 3 SP1 4 CPX 3 SP1 4 AND 3 SP1 4 BIT 3 SP1 4 LDA 3 SP1 4 STA 3 SP1 4 EOR 3 SP1 4 ADC 3 SP1 4 ORA 3 SP1 4 ADD 3 SP1
IX F
0 5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR
1 4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR
0 1 2 3 4 5 6 7 8 9 A B C D E F
4 1 NEG NEGA 2 DIR 1 INH 5 4 CBEQ CBEQA 3 DIR 3 IMM 5 MUL 1 INH 4 1 COM COMA 2 DIR 1 INH 4 1 LSR LSRA 2 DIR 1 INH 4 3 STHX LDHX 2 DIR 3 IMM 4 1 ROR RORA 2 DIR 1 INH 4 1 ASR ASRA 2 DIR 1 INH 4 1 LSL LSLA 2 DIR 1 INH 4 1 ROL ROLA 2 DIR 1 INH 4 1 DEC DECA 2 DIR 1 INH 5 3 DBNZ DBNZA 3 DIR 2 INH 4 1 INC INCA 2 DIR 1 INH 3 1 TST TSTA 2 DIR 1 INH 5 MOV 3 DD 3 1 CLR CLRA 2 DIR 1 INH
5 3 NEG NEG 3 SP1 1 IX 6 4 CBEQ CBEQ 4 SP1 2 IX+ 2 DAA 1 INH 5 3 COM COM 3 SP1 1 IX 5 3 LSR LSR 3 SP1 1 IX 4 CPHX 2 DIR 5 3 ROR ROR 3 SP1 1 IX 5 3 ASR ASR 3 SP1 1 IX 5 3 LSL LSL 3 SP1 1 IX 5 3 ROL ROL 3 SP1 1 IX 5 3 DEC DEC 3 SP1 1 IX 6 4 DBNZ DBNZ 4 SP1 2 IX 5 3 INC INC 3 SP1 1 IX 4 2 TST TST 3 SP1 1 IX 4 MOV 2 IX+D 4 2 CLR CLR 3 SP1 1 IX
7 3 RTI BGE 1 INH 2 REL 4 3 RTS BLT 1 INH 2 REL 3 BGT 2 REL 9 3 SWI BLE 1 INH 2 REL 2 2 TAP TXS 1 INH 1 INH 1 2 TPA TSX 1 INH 1 INH 2 PULA 1 INH 2 1 PSHA TAX 1 INH 1 INH 2 1 PULX CLC 1 INH 1 INH 2 1 PSHX SEC 1 INH 1 INH 2 2 PULH CLI 1 INH 1 INH 2 2 PSHH SEI 1 INH 1 INH 1 1 CLRH RSP 1 INH 1 INH 1 NOP 1 INH 1 STOP * 1 INH 1 1 WAIT TXA 1 INH 1 INH
3 SUB 2 DIR 3 CMP 2 DIR 3 SBC 2 DIR 3 CPX 2 DIR 3 AND 2 DIR 3 BIT 2 DIR 3 LDA 2 DIR 3 STA 2 DIR 3 EOR 2 DIR 3 ADC 2 DIR 3 ORA 2 DIR 3 ADD 2 DIR 2 JMP 2 DIR 4 4 BSR JSR 2 REL 2 DIR 2 3 LDX LDX 2 IMM 2 DIR 2 3 AIX STX 2 IMM 2 DIR
MSB LSB
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
4 4 4 4 4 4 4 4 4 4 4 4
4 4
3 SUB 2 IX1 3 CMP 2 IX1 3 SBC 2 IX1 3 CPX 2 IX1 3 AND 2 IX1 3 BIT 2 IX1 3 LDA 2 IX1 3 STA 2 IX1 3 EOR 2 IX1 3 ADC 2 IX1 3 ORA 2 IX1 3 ADD 2 IX1 3 JMP 2 IX1 5 JSR 2 IX1 5 3 LDX LDX SP2 2 IX1 5 3 STX STX SP2 2 IX1
2 SUB 1 IX 2 CMP 1 IX 2 SBC 1 IX 2 CPX 1 IX 2 AND 1 IX 2 BIT 1 IX 2 LDA 1 IX 2 STA 1 IX 2 EOR 1 IX 2 ADC 1 IX 2 ORA 1 IX 2 ADD 1 IX 2 JMP 1 IX 4 JSR 1 IX 4 2 LDX LDX 3 SP1 1 IX 4 2 STX STX 3 SP1 1 IX
Inherent REL Relative Immediate IX Indexed, No Offset Direct IX1 Indexed, 8-Bit Offset Extended IX2 Indexed, 16-Bit Offset Direct-Direct IMD Immediate-Direct Indexed-Direct DIX+ Direct-Indexed *Pre-byte for stack pointer indexed instructions
INH IMM DIR EXT DD IX+D
SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment
0
High Byte of Opcode in Hexadecimal
Low Byte of Opcode in Hexadecimal
0
5 Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes / Addressing Mode
Technical Data -- MC68HC08JB1
Section 7. Oscillator (OSC)
7.1 Contents
7.2 7.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Oscillator External Connections . . . . . . . . . . . . . . . . . . . . . . . . 72
7.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . 73 7.4.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . 73 7.4.3 Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . . . 73 7.4.4 External Clock Source (OSCXCLK) . . . . . . . . . . . . . . . . . . . 73 7.4.5 Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 7.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.2 Introduction
The oscillator circuit is designed for use with crystals or ceramic resonators. The oscillator circuit generates the crystal clock signal. The crystal oscillator output signal passes through the clock doubler. OSCXCLK is the output signal of the clock doubler. OSCXCLK is divided by two before being passed on to the system integration module (SIM) for bus clock generation. Figure 7-1 shows the structure of the oscillator. The oscillator requires various external components.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Oscillator (OSC)
Technical Data 71
Oscillator (OSC) 7.3 Oscillator External Connections
In its typical configuration, the oscillator requires five external components. The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 7-1. This figure shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: * * * * * Crystal, X1 Fixed capacitor, C1 Tuning capacitor, C2 (can also be a fixed capacitor) Feedback resistor, RB Series resistor, RS (optional)
FROM SIM
TO USB
TO SIM
TO SIM
CLOCK DOUBLER SIMOSCEN
OSCXCLK
/2
OSCOUT
MCU OSC1 RB OSC2
RS* X1
C1
C2
* RS can be 0 (shorted) when used with higher-frequency crystals. Refer to manufacturer's data.
Figure 7-1. Oscillator External Connections
Technical Data 72 Oscillator (OSC)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Oscillator (OSC) I/O Signals
The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines and may not be required for all ranges of operation, especially with high-frequency crystals. Refer to the crystal manufacturer's data for more information.
7.4 I/O Signals
The following paragraphs describe the oscillator input/output (I/O) signals.
7.4.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier.
7.4.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output of the crystal oscillator inverting amplifier.
7.4.3 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator.
7.4.4 External Clock Source (OSCXCLK) The crystal oscillator output signal passes through the clock doubler and OSCXCLK is the output signal of the clock doubler. OSCXCLK runs at twice the speed of the crystal (fXCLK). Figure 7-1 shows only the logical relation of OSCXCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of OSCXCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of OSCXCLK can be unstable at startup.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Oscillator (OSC)
Technical Data 73
Oscillator (OSC)
7.4.5 Oscillator Out (OSCOUT) The clock driven to the SIM is OSCXCLK. This signal is driven to the SIM for generation of the bus clocks used by the CPU and other modules on the MCU. OSCOUT will be divided again in the SIM and results in the internal bus frequency being one forth of the OSCXCLK frequency or one half of the crystal frequency.
7.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-powerconsumption standby modes.
7.5.1 Wait Mode The WAIT instruction has no effect on the oscillator logic. OSCXCLK continues to drive to the SIM module.
7.5.2 Stop Mode The STOP instruction disables the OSCXCLK output.
Technical Data 74 Oscillator (OSC)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Technical Data -- MC68HC08JB1
Section 8. System Integration Module (SIM)
8.1 Contents
8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . 78 8.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 8.3.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . 78 8.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . 79 8.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . . 79 8.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . 80 8.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . . 82 8.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . 83 8.4.2.6 Universal Serial Bus Reset . . . . . . . . . . . . . . . . . . . . . . . 83 8.4.2.7 Registers Values After Different Resets. . . . . . . . . . . . . . 84 8.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . 85 8.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . . 85 8.5.3 SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . .85 8.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.6.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.6.2 Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 89 8.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . 90 8.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.7
MC68HC08JB1 -- Rev. 2.0 MOTOROLA System Integration Module (SIM)
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Technical Data 75
System Integration Module (SIM)
8.7.1 8.7.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8.8.1 Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
8.2 Introduction
This section describes the system integration module (SIM), which supports up to 8 external and/or internal interrupts. Together with the CPU, the SIM controls all MCU activities. The SIM is a system state controller that coordinates CPU and exception timing. A block diagram of the SIM is shown in Figure 8-1. Figure 8-2 is a summary of the SIM I/O registers. The SIM is responsible for: * Bus clock generation and control for CPU and peripherals - Stop/wait/reset entry and recovery - Internal clock control * * Master reset control, including power-on reset (POR) and COP timeout Interrupt control: - Acknowledge timing - Arbitration control timing - Vector address generation * * CPU enable/disable timing Modular architecture expandable to 128 interrupt sources
Technical Data 76 System Integration Module (SIM)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
System Integration Module (SIM) Introduction
MODULE STOP MODULE WAIT STOP/WAIT CONTROL CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO OSCILLATOR) SIM COUNTER COP CLOCK
OSCXCLK (FROM CLOCK DOUBLER) OSCOUT (FROM CLOCK DOUBLER) /2 VDD CLOCK CONTROL CLOCK GENERATORS INTERNAL CLOCKS
INTERNAL PULL-UP
RESET PIN LOGIC
POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER MASTER RESET CONTROL
ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) LVI RESET (FROM LVI MODULE) USB RESET (FROM USB MODULE)
RESET
INTERRUPT CONTROL AND PRIORITY DECODE
INTERRUPT SOURCES CPU INTERFACE
Figure 8-1. SIM Block Diagram Table 8-1. SIM Module Signal Name Conventions
Signal Name OSCXCLK OSCOUT IAB IDB PORRST IRST R/W Description Clock doubler output which has twice the frequency of OSC1 from the oscillator The OSCXCLK frequency divided by two. This signal is again divided by two in the SIM to generate the internal bus clocks. (Bus clock = OSCXCLK / 4 = fOSC / 2) Internal address bus Internal data bus Signal from the power-on reset module to the SIM Internal reset signal Read/write signal
MC68HC08JB1 -- Rev. 2.0 MOTOROLA System Integration Module (SIM)
Technical Data 77
System Integration Module (SIM)
Addr.
Register Name Read: Reset Status Register Write: (RSR) POR:
Bit 7 POR
6 PIN
5 COP
4 ILOP
3 ILAD
2 USB
1 LVI
Bit 0 0
$FE01
1 IF6 R 0
0 IF5 R 0
0 IF4 R 0
0 IF3 R 0
0 IF2 R 0
0 IF1 R 0
0 0 R 0
0 0 R 0
Read: Interrupt Status Register 1 $FE04 Write: (INT1) Reset:
Figure 8-2. SIM I/O Register Summary
8.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, OSCOUT, as shown in Figure 8-3.
FROM CLOCK DOUBLER FROM CLOCK DOUBLER
OSCXCLK OSCOUT
SIM COUNTER /2 BUS CLOCK GENERATORS
SIM
Figure 8-3. SIM Clock Signals 8.3.1 Bus Timing In user mode, the internal bus frequency is the oscillator frequency divided by two. 8.3.2 Clock Startup from POR or LVI Reset When the power-on reset (POR) module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 OSCXCLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout.
Technical Data 78 System Integration Module (SIM) MC68HC08JB1 -- Rev. 2.0 MOTOROLA
System Integration Module (SIM) Reset and System Initialization
8.3.3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode by an interrupt or reset, the SIM allows OSCXCLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 2048 OSCXCLK cycles. (See 8.7.2 Stop Mode.) In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
8.4 Reset and System Initialization
The MCU has these reset sources: * * * * * * * Power-on reset module (POR) External reset pin (RST) Computer operating properly module (COP) Illegal opcode Illegal address Universal serial bus module (USB) Low-voltage inhibit module (LVI)
All of these resets produce the vector $FFFE-FFFF ($FEFE-FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 8.5 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the reset status register (RSR). (See 8.8 SIM Registers.)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA System Integration Module (SIM)
Technical Data 79
System Integration Module (SIM)
8.4.1 External Pin Reset The RST pin circuit includes an internal pullup device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the reset status register (RSR) is set as long as RST is held low for a minimum of 67 OSCXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See Table 8-2 for details. Figure 8-4 shows the relative timing. Table 8-2. PIN Bit Set Timing
Reset Type POR/LVI All others Number of Cycles Required to Set PIN 4163 (4096 + 64 + 3) 67 (64 + 3)
OSCOUT
RST
IAB
PC
VECT H
VECT L
Figure 8-4. External Reset Timing
8.4.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 OSCXCLK cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles. (See Figure 8-5.) An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, the USB module or POR. (See Figure 8-6 . Sources of Internal Reset.)
NOTE:
For LVI or POR resets, the SIM cycles through 4096 OSCXCLK cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 8-5.
Technical Data 80 System Integration Module (SIM)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
System Integration Module (SIM) Reset and System Initialization
IRST
RST
RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES
OSCXCLK
IAB
VECTOR HIGH
Figure 8-5. Internal Reset Timing The COP reset is asynchronous to the bus clock.
ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST POR LVI USB
INTERNAL RESET
Figure 8-6. Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. 8.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 OSCXCLK cycles. Sixty-four OSCXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, the following events occur: * * * * A POR pulse is generated. The internal reset signal is asserted. The SIM enables the oscillator to drive OSCXCLK. Internal clocks to the CPU and modules are held inactive for 4096 OSCXCLK cycles to allow stabilization of the oscillator.
Technical Data System Integration Module (SIM) 81
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
System Integration Module (SIM)
* * The RST pin is driven low during the oscillator stabilization time. The POR bit of the reset status register (RSR) is set and all other bits in the register are cleared.
OSC1
PORRST 4096 CYCLES OSCXCLK 32 CYCLES 32 CYCLES
OSCOUT
RST
IAB
$FFFE
$FFFF
Figure 8-7. POR Recovery 8.4.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the reset status register (RSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module timeout, write any value to location $FFFF. Writing to location $FFFF clears the COP counter and stages 12 through 5 of the SIM counter. The SIM counter output, which occurs at least every 212 - 24 OSCXCLK cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first timeout. The COP module is disabled if the RST pin or the IRQ pin is held at VDD + VHI while the MCU is in monitor mode. The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise.
Technical Data 82 System Integration Module (SIM) MC68HC08JB1 -- Rev. 2.0 MOTOROLA
System Integration Module (SIM) Reset and System Initialization
8.4.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the reset status register (RSR) and causes a reset. If the stop enable bit, STOP, in the mask option register is logic 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 8.4.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the reset status register (RSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources. 8.4.2.5 Low-Voltage Inhibit (LVI) Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the LVI reset voltage, VTRIP. The LVI bit in the reset status register (RSR) is set, and the external reset pin (RST) is held low while the SIM counter counts out 4096 OSCXCLK cycles. Sixty-four OSCXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the RST pin for all internal reset sources. 8.4.2.6 Universal Serial Bus Reset The USB module will detect a reset signaled on the bus by the presence of an extended SE0 at the USB data pins of a device. The MCU seeing a single-ended 0 on its USB data inputs for more than 2.5s treats that signal as a reset. After the reset is removed, the device will be in the attached, but not yet addressed or configured, state (refer to Section 9.1 USB Devices of the Universal Serial Bus Specification Rev. 1.1). The device must be able to accept the device address via a SET_ADDRESS
MC68HC08JB1 -- Rev. 2.0 MOTOROLA System Integration Module (SIM) Technical Data 83
System Integration Module (SIM)
command (refer to Section 9.4 of the Universal Serial Bus Specification Rev. 1.1) no later than 10ms after the reset is removed. USB reset can be disabled to generate an internal reset, instead, a USB interrupt can be generated. (See Section 5. Configuration Register (CONFIG).)
NOTE:
USB reset is disabled when the USB module is disabled by clearing the USBEN bit of the USB Address Register (UADDR).
8.4.2.7 Registers Values After Different Resets Some registers are reset by POR or LVI reset only. Table 8-3 shows the registers or register bits which are unaffected by normal resets. Table 8-3. Registers not Affected by Normal Reset
Bits URSTD, LVIDIS USBEN PULLEN All All All All All DDRA7 Registers CONFIG UADDR UCR3 USR0, USR1 UE0D0-UE0D7 UE1D0-UE1D7 UE2D0-UE2D7 PTA, PTC, PTD, and PTE DDRA After Reset (except POR or LVI) Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected After POR or LVI 0 0 0 Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate 0
8.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescalar for the computer operating properly module (COP). The SIM counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP module. The SIM counter is clocked by the falling edge of OSCXCLK.
Technical Data 84 System Integration Module (SIM) MC68HC08JB1 -- Rev. 2.0 MOTOROLA
System Integration Module (SIM) Exception Control
8.5.1 SIM Counter During Power-On Reset The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock state machine.
8.5.2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the configuration register (CONFIG). If the SSREC bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 OSCXCLK cycles down to 2048 OSCXCLK cycles. This is ideal for applications using canned oscillators that do not require long startup times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared in the configuration register (CONFIG).
8.5.3 SIM Counter and Reset States External reset has no effect on the SIM counter. (See 8.7.2 Stop Mode for details.) The SIM counter is free-running after all reset states. (See 8.4.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences.)
8.6 Exception Control
Normal, sequential program execution can be changed in two different ways: * Interrupts - Maskable hardware CPU interrupts - Non-maskable software interrupt instruction (SWI) * Reset
MC68HC08JB1 -- Rev. 2.0 MOTOROLA System Integration Module (SIM)
Technical Data 85
System Integration Module (SIM)
8.6.1 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event. Figure 8-8 flow charts the handling of system interrupts.
FROM RESET
YES
BIT SET? IIBIT SET? NO IRQ INTERRUPT ? NO USB INTERRUPT ? NO YES
YES
OTHER INTERRUPTS ? NO
YES
STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT INSTRUCTION
SWI INSTRUCTION ? NO RTI INSTRUCTION ? NO
YES
YES
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
Figure 8-8. Interrupt Processing
Technical Data 86 System Integration Module (SIM) MC68HC08JB1 -- Rev. 2.0 MOTOROLA
System Integration Module (SIM) Exception Control
Interrupts are latched and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced or the I bit is cleared. At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 8-9 shows interrupt entry timing. Figure 8-10 shows interrupt recovery timing.
MODULE INTERRUPT I BIT
IAB
DUMMY
SP
SP - 1
SP - 2
SP - 3
SP - 4
VECT H
VECT L
START ADDR
IDB
DUMMY
PC - 1[7:0] PC - 1[15:8]
X
A
CCR
V DATA H
V DATA L
OPCODE
R/W
Figure 8-9. Interrupt Entry
MODULE INTERRUPT I BIT
IAB
SP - 4
SP - 3
SP - 2
SP - 1
SP
PC
PC + 1
IDB
CCR
A
X
PC - 1[15:8] PC - 1[7:0]
OPCODE
OPERAND
R/W
Figure 8-10. Interrupt Recovery
MC68HC08JB1 -- Rev. 2.0 MOTOROLA System Integration Module (SIM)
Technical Data 87
System Integration Module (SIM)
8.6.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 8-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.
CLI LDA #$FF BACKGROUND ROUTINE
INT1
PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI
INT2
PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI
Figure 8-11. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation.
NOTE:
To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine.
MC68HC08JB1 -- Rev. 2.0 System Integration Module (SIM) MOTOROLA
Technical Data 88
System Integration Module (SIM) Exception Control
8.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register.
NOTE:
A software interrupt pushes PC onto the stack. A software interrupt does not push PC-1, as a hardware interrupt does.
8.6.2 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 8-4 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging. Table 8-4. Interrupt Sources
Source SWI Instruction USB Reset Interrupt USB Endpoint 0 Transmit USB Endpoint 0 Receive USB Endpoint 1 Transmit USB Endpoint 2 Transmit USB End of Packet USB Resume Interrupt IRQ Interrupt (IRQ, PTE4) TIM Channel 0 TIM Channel 1 TIM Overflow Keyboard Pins Flags -- RSTF TXD0F RXD0F TXD1F TXD2F EOPF RESUMF IRQF PTE4IF CH0F CH1F TOF KEYF Mask(1) -- URSTD TXD0IE RXD0IE TXD1IE TXD2IE EOPIE -- IMASK CH0IE CH1IE TOIE IMASKK IF1 IF3 IF4 IF5 IF6 2 3 4 5 6 $FFF8-$FFF9 $FFF6-$FFF7 $FFF4-$FFF5 $FFF2-$FFF3 $FFF0-$FFF1 IF2 1 $FFFA-$FFFB INT Register Flag -- Priority(2) 0 Vector Address $FFFC-$FFFD
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction. 2. 0 = highest priority
MC68HC08JB1 -- Rev. 2.0 MOTOROLA System Integration Module (SIM)
Technical Data 89
System Integration Module (SIM)
8.6.2.1 Interrupt Status Register 1
Address: $FE04 Bit 7 Read: Write: Reset: IF6 R 0 R 6 IF5 R 0 = Reserved 5 IF4 R 0 4 IF3 R 0 3 IF2 R 0 2 IF1 R 0 1 0 R 0 Bit 0 0 R 0
Figure 8-12. Interrupt Status Register 1 (INT1) IF6-IF1 -- Interrupt Flags 1-6 These flags indicate the presence of interrupt requests from the sources shown in Table 8-4. 1 = Interrupt request present 0 = No interrupt request present Bit 0 and Bit 1 -- Always read 0
8.6.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated.
8.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low-powerconsumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described here. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur.
8.7.1 Wait Mode In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 8-13 shows the timing for wait mode entry.
Technical Data 90 System Integration Module (SIM) MC68HC08JB1 -- Rev. 2.0 MOTOROLA
System Integration Module (SIM) Low-Power Modes
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode can also be exited by a reset. If the COP disable bit, COPD, in the mask option register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode.
IAB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 8-13. Wait Mode Entry Timing Figure 8-14 and Figure 8-15 show the timing for WAIT recovery.
IAB
$6E0B
$6E0C
$00FF
$00FE
$00FD
$00FC
IDB
$A6
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT NOTE: EXITSTOPWAIT = RST pin or CPU interrupt
Figure 8-14. Wait Recovery from Interrupt
MC68HC08JB1 -- Rev. 2.0 MOTOROLA System Integration Module (SIM)
Technical Data 91
System Integration Module (SIM)
32 CYCLES IAB $6E0B
32 CYCLES RST VCT H RST VCT L
IDB
$A6
$A6
$A6
RST
OSCXCLK
Figure 8-15. Wait Recovery from Internal Reset
8.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset also causes an exit from stop mode. The SIM disables the oscillator signals (OSCOUT and OSCXCLK) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register (CONFIG). If SSREC is set, stop recovery is reduced from the normal delay of 4096 OSCXCLK cycles down to 2048. This is ideal for applications using canned oscillators that do not require long startup times from stop mode.
NOTE:
External crystal applications should use the full stop recovery time by clearing the SSREC bit. The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 8-16 shows stop mode entry timing.
NOTE:
To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0.
Technical Data 92 System Integration Module (SIM)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
System Integration Module (SIM) SIM Registers
CPUSTOP
IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 8-16. Stop Mode Entry Timing
STOP RECOVERY PERIOD OSCXCLK
INT
IAB
STOP +1
STOP + 2
STOP + 2
SP
SP - 1
SP - 2
SP - 3
Figure 8-17. Stop Mode Recovery from Interrupt
8.8 SIM Registers
The SIM has one reset register.
8.8.1 Reset Status Register This register contains seven flags that show the source of the last reset. All flag bits are cleared automatically following a read of the register. The register is initialized on power-up as shown with the POR bit set and all other bits cleared. However, during a POR or any other internal reset, the RST pin is pulled low. After the pin is released, it will be sampled 32 XCLK cycles later. If the pin is not above a VIH at that time, then the PIN bit in the RSR may be set in addition to whatever other bits are set.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA System Integration Module (SIM)
Technical Data 93
System Integration Module (SIM)
Address:
$FE01 Bit 7 6 PIN 5 COP 4 ILOP 3 ILAD 2 USB 1 LVI Bit 0 0
Read: Write: POR:
POR
1
0
0
0
0
0
0
0
= Unimplemented
Figure 8-18. Reset Status Register (RSR) POR -- Power-On Reset Bit 1 = A POR has occurred 0 = Read of RSR PIN -- External Reset Bit 1 = An external reset has occurred since the last read of the RSR 0 = Read of RSR COP -- Computer Operating Properly Reset Bit 1 = A COP reset has occurred since the last read of the RSR 0 = POR or read of RSR ILOP -- Illegal Opcode Reset Bit An illegal opcode reset has occurred since the last read of the RSR 0 = POR or read of RSR ILAD -- Illegal Address Reset Bit (opcode fetches only) 1 = An illegal address reset has occurred since the last read of the RSR 0 = POR or read of RSR USB -- Universal Serial Bus Reset Bit 1 = Last reset caused by the USB module 0 = POR or read of RSR LVI -- Low voltage inhibit Reset Bit 1 = A LVI reset has occurred since the last read of PSR 0 = POR or read of RSR
Technical Data 94 System Integration Module (SIM)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Technical Data -- MC68HC08JB1
Section 9. Universal Serial Bus Module (USB)
9.1 Contents
9.2 9.3 9.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 9.5.1 USB Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 9.5.1.1 Sync Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 9.5.1.2 Packet Identifier Field . . . . . . . . . . . . . . . . . . . . . . . . . .105 9.5.1.3 Address Field (ADDR) . . . . . . . . . . . . . . . . . . . . . . . . . .106 9.5.1.4 Endpoint Field (ENDP). . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.5.1.5 Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . . 106 9.5.1.6 End-of-Packet (EOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.5.2 Reset Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 9.5.3 Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.5.4 Resume After Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.5.4.1 Host Initiated Resume . . . . . . . . . . . . . . . . . . . . . . . . . .109 9.5.4.2 USB Reset Signalling. . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.5.4.3 Remote Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9.5.5 Low-Speed Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.6 Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
9.7 Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.7.1 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.7.2 USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.7.2.1 Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . 112 9.7.2.2 Low Speed (1.5 Mbps) Driver Characteristics . . . . . . . . 112 9.7.2.3 Receiver Data Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.7.2.4 Data Source Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9.7.2.5 Data Signal Rise and Fall Time . . . . . . . . . . . . . . . . . . .114
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB) Technical Data 95
Universal Serial Bus Module (USB)
9.7.3 USB Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
9.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.8.1 USB Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.8.2 USB Interrupt Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . .117 9.8.3 USB Interrupt Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . .118 9.8.4 USB Interrupt Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . .121 9.8.5 USB Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9.8.6 USB Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.8.7 USB Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.8.8 USB Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.8.9 USB Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.8.10 USB Status Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.8.11 USB Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.8.12 USB Endpoint 0 Data Registers . . . . . . . . . . . . . . . . . . . . . 131 9.8.13 USB Endpoint 1 Data Registers . . . . . . . . . . . . . . . . . . . . . 132 9.8.14 USB Endpoint 2 Data Registers . . . . . . . . . . . . . . . . . . . . . 133 9.9 USB Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.9.1 USB End-of-Transaction Interrupt . . . . . . . . . . . . . . . . . . .134 9.9.1.1 Receive Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . . .135 9.9.1.2 Transmit Control Endpoint 0 . . . . . . . . . . . . . . . . . . . . . 137 9.9.1.3 Transmit Endpoint 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.9.1.4 Transmit Endpoint 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.9.2 Resume Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.9.3 End-of-Packet Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
9.2 Introduction
This section describes the universal serial bus (USB) module. The USB module is designed to serve as a low-speed (LS) USB device per the Universal Serial Bus Specification Rev 1.1. Control and interrupt data transfers are supported. Endpoint 0 functions as a transmit/receive control endpoint; endpoint 1 functions as interrupt transmit endpoint; endpoint 2 functions as interrupt transmit endpoint.
Technical Data 96 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) Features
9.3 Features
Features of the USB module include: * * * * * * * Full Universal Serial Bus Specification 1.1 low-speed functions 1.5 Mbps data rate On-chip 3.3V regulator Endpoint 0 with 8-byte transmit buffer and 8-byte receive buffer Endpoint 1 with 8-byte transmit buffer Endpoint 2 with 8-byte transmit buffer USB data control logic: - Control endpoint 0 and interrupt endpoints 1 and 2 - Packet decoding/generation - CRC generation and checking - NRZI (Non-Return-to Zero Inserted) encoding/decoding - Bit-stuffing * USB reset options: - Internal MCU reset generation - CPU interrupt request generation * * Suspend and resume operations, with remote wakeup support USB-generated interrupts: - Transaction interrupt driven - Resume interrupt - End-of-packet interrupt - USB reset * STALL, NAK, and ACK handshake generation
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 97
Universal Serial Bus Module (USB) 9.4 Pin Name Conventions
The USB share two I/O pins with two port E I/O pins. The full name of the USB I/O pin is listed in Table 9-1. The generic pin name appear in the text that follows. Table 9-1. USB Module Pin Name Conventions
USB Generic Pin Names: Full USB Pin Names: D+ PTE3/D+ D- PTE4/D-
Addr.
Register Name
Bit 7
6 0 RSTFR 0 STALL2 0 0 TX1STR
5 0 TXD2FR 0 TX2E 0
4 0
3 0
2 0
1 0
Bit 0 0 RXD0FR 0 TP2SIZ0 0
$0018
Read: 0 USB Interrupt Register 2 Write: EOPFR (UIR2) Reset: 0 Read: USB Control Register 2 Write: (UCR2) Reset: Read: USB Control Register 3 Write: (UCR3) Reset: T2SEQ 0 TX1ST
TXD1FR RESUMFR TXD0FR 0 0 0 TP2SIZ3 0 0 0 TP2SIZ2 0 0 TP2SIZ1 0
$0019
0
$001A
OSTALL0 ISTALL0 0 0
PULLEN ENABLE2 ENABLE1 0* 0 0
0
0
0
* PULLEN bit is reset by POR or LVI reset only. Read: USB Control Register 4 Write: (UCR4) Reset: 0 0 0 0 0 FUSBO 0 UE0R02 UE0T02 FDP 0 UE0R01 UE0T01 FDM 0 UE0R00 UE0T00
$001B
0
0 UE0R06 UE0T06
0 UE0R05 UE0T05
0 UE0R04 UE0T04
0 UE0R03 UE0T03
$0020
Read: UE0R07 USB Endpoint 0 Data Register 0 Write: UE0T07 (UE0D0) Reset: Read: UE0R17 USB Endpoint 0 Data Register 1 Write: UE0T17 (UE0D1) Reset:
Unaffected by reset UE0R16 UE0T16 UE0R15 UE0T15 UE0R14 UE0T14 UE0R13 UE0T13 UE0R12 UE0T12 UE0R11 UE0T11 UE0R10 UE0T10
$0021
Unaffected by reset = Unimplemented U = Unaffected by reset
Figure 9-1. USB I/O Register Summary (Sheet 1 of 4)
Technical Data 98 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) Pin Name Conventions
Addr.
Register Name
Bit 7
6 UE0R26 UE0T26
5 UE0R25 UE0T25
4 UE0R24 UE0T24
3 UE0R23 UE0T23
2 UE0R22 UE0T22
1 UE0R21 UE0T21
Bit 0 UE0R20 UE0T20
$0022
Read: UE0R27 USB Endpoint 0 Data Register 2 Write: UE0T27 (UE0D2) Reset: Read: UE0R37 USB Endpoint 0 Data Register 3 Write: UE0T37 (UE0D3) Reset: Read: UE0R47 USB Endpoint 0 Data Register 4 Write: UE0T47 (UE0D4) Reset: Read: UE0R57 USB Endpoint 0 Data Register 5 Write: UE0T57 (UE0D5) Reset: Read: UE0R67 USB Endpoint 0 Data Register 6 Write: UE0T67 (UE0D6) Reset: Read: UE0R77 USB Endpoint 0 Data Register 7 Write: UE0T77 (UE0D7) Reset: Read: USB Endpoint 1 Data Register 0 Write: UE1T07 (UE1D0) Reset: Read: USB Endpoint 1 Data Register 1 Write: UE1T17 (UE1D1) Reset: Read: USB Endpoint 1 Data Register 2 Write: UE1T27 (UE1D2) Reset: Read: USB Endpoint 1 Data Register 3 Write: UE1T37 (UE1D3) Reset:
Unaffected by reset UE0R36 UE0T36 UE0R35 UE0T35 UE0R34 UE0T34 UE0R33 UE0T33 UE0R32 UE0T32 UE0R31 UE0T31 UE0R30 UE0T30
$0023
Unaffected by reset UE0R46 UE0T46 UE0R45 UE0T45 UE0R44 UE0T44 UE0R43 UE0T43 UE0R42 UE0T42 UE0R41 UE0T41 UE0R40 UE0T40
$0024
Unaffected by reset UE0R56 UE0T56 UE0R55 UE0T55 UE0R54 UE0T54 UE0R53 UE0T53 UE0R52 UE0T52 UE0R51 UE0T51 UE0R50 UE0T50
$0025
Unaffected by reset UE0R66 UE0T66 UE0R65 UE0T65 UE0R64 UE0T64 UE0R63 UE0T63 UE0R62 UE0T62 UE0R61 UE0T61 UE0R60 UE0T60
$0026
Unaffected by reset UE0R76 UE0T76 UE0R75 UE0T75 UE0R74 UE0T74 UE0R73 UE0T73 UE0R72 UE0T72 UE0R71 UE0T71 UE0R70 UE0T70
$0027
Unaffected by reset
$0028
UE1T06
UE1T05
UE1T04
UE1T03
UE1T02
UE1T01
UE1T00
Unaffected by reset
$0029
UE1T16
UE1T15
UE1T14
UE1T13
UE1T12
UE1T11
UE1T10
Unaffected by reset
$002A
UE1T26
UE1T25
UE1T24
UE1T23
UE1T22
UE1T21
UE1T20
Unaffected by reset
$002B
UE1T36
UE1T35
UE1T34
UE1T33
UE1T32
UE1T31
UE1T30
Unaffected by reset = Unimplemented U = Unaffected by reset
Figure 9-1. USB I/O Register Summary (Sheet 2 of 4)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 99
Universal Serial Bus Module (USB)
Addr. $002C
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: USB Endpoint 1 Data Register 4 Write: UE1T47 (UE1D4) Reset: Read: USB Endpoint 1 Data Register5 Write: UE1T57 (UE1D5) Reset: Read: USB Endpoint 1 Data Register 6 Write: UE1T67 (UE1D6) Reset: Read: USB Endpoint 1 Data Register 7 Write: UE1T77 (UE1D7) Reset: Read: USB Endpoint 2 Data Register 0 Write: UE2T07 (UE2D0) Reset: Read: USB Endpoint 2 Data Register 1 Write: UE2T17 (UE2D1) Reset: Read: USB Endpoint 2 Data Register 2 Write: UE2T27 (UE2D2) Reset: Read: USB Endpoint 2 Data Register 3 Write: UE2T37 (UE2D3) Reset: Read: USB Endpoint 2 Data Register 4 Write: UE2T47 (UE2D4) Reset: Read: USB Endpoint 2 Data Register 5 Write: UE2T57 (UE2D5) Reset:
UE1T46
UE1T45
UE1T44
UE1T43
UE1T42
UE1T41
UE1T40
Unaffected by reset
$002D
UE1T56
UE1T55
UE1T54
UE1T53
UE1T52
UE1T51
UE1T50
Unaffected by reset
$002E
UE1T66
UE1T65
UE1T64
UE1T63
UE1T62
UE1T61
UE1T60
Unaffected by reset
$002F
UE1T76
UE1T75
UE1T74
UE1T73
UE1T72
UE1T71
UE1T70
Unaffected by reset
$0030
UE2T06
UE2T05
UE2T04
UE2T03
UE2T02
UE2T01
UE2T00
Unaffected by reset
$0031
UE2T16
UE2T15
UE2T14
UE2T13
UE2T12
UE2T11
UE2T10
Unaffected by reset
$0032
UE2T26
UE2T25
UE2T24
UE2T23
UE2T22
UE2T21
UE2T20
Unaffected by reset
$0033
UE2T36
UE2T35
UE2T34
UE2T33
UE2T32
UE2T31
UE2T30
Unaffected by reset
$0034
UE2T46
UE2T45
UE2T44
UE2T43
UE2T42
UE2T41
UE2T40
Unaffected by reset
$0035
UE2T56
UE2T55
UE2T54
UE2T53
UE2T52
UE2T51
UE2T50
Unaffected by reset = Unimplemented U = Unaffected by reset
Figure 9-1. USB I/O Register Summary (Sheet 3 of 4)
Technical Data 100 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) Pin Name Conventions
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$0036
Read: USB Endpoint 2 Data Register 6 Write: UE2T67 (UE2D6) Reset: Read: USB Endpoint 2 Data Register 7 Write: UE2T77 (UE2D7) Reset: Read: USBEN USB Address Register Write: (UADDR) Reset: 0*
UE2T66
UE2T65
UE2T64
UE2T63
UE2T62
UE2T61
UE2T60
Unaffected by reset
$0037
UE2T76
UE2T75
UE2T74
UE2T73
UE2T72
UE2T71
UE2T70
Unaffected by reset UADD6 0 UADD5 0 UADD4 0 UADD3 0 UADD2 0 UADD1 0 UADD0 0
$0038
* USBEN bit is reset by POR or LVI reset only. Read: USB Interrupt Register 0 Write: (UIR0) Reset: Read: USB Interrupt Register 1 Write: (UIR1) Reset: Read: USB Control Register 0 Write: (UCR0) Reset: Read: USB Control Register 1 Write: (UCR1) Reset: EOPIE 0 EOPF SUSPND 0 RSTF TXD2IE 0 TXD2F 0 TXD1IE 0 TXD1F 0 TXD0IE 0 TXD0F RXD0IE 0 RXD0F
$0039
0 0
0 RESUMF
$003A
0 T0SEQ 0 T1SEQ 0
0 0
0 TX0E 0 TX1E 0 0
0 RX0E 0
0 TP0SIZ3 0
0 TP0SIZ2 0 TP1SIZ2 0 RP0SIZ2
0 TP0SIZ1 0 TP1SIZ1 0 RP0SIZ1
0 TP0SIZ0 0 TP1SIZ0 0 RP0SIZ0
$003B
0 STALL1 0 SETUP
$003C
FRESUM TP1SIZ3 0 0 0 RP0SIZ3
$003D
Read: R0SEQ USB Status Register 0 Write: (USR0) Reset: Read: USB Status Register 1 Write: (USR1) Reset: 0
Unaffected by reset TXACK TXNAK TXSTL 0 0 0 0
$003E
0
0
0
0
0
0
0
0
= Unimplemented
U = Unaffected by reset
Figure 9-1. USB I/O Register Summary (Sheet 4 of 4)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 101
Universal Serial Bus Module (USB) 9.5 Functional Description
Figure 9-2 shows the block diagram of the USB module. The USB module manages communications between the host and the USB function. The module is partitioned into three functional blocks. These blocks consist of a dual-function transceiver, the USB control logic, and the endpoint registers. The blocks are further detailed later in this section (see 9.7 Hardware Description).
RCV USB CONTROL LOGIC VPOUT VMOUT VPIN VMIN TRANSCEIVER D+ USB UPSTREAM PORT
D-
CPU BUS
USB REGISTERS
Figure 9-2. USB Block Diagram
Technical Data 102 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) Functional Description
9.5.1 USB Protocol Figure 9-3 shows the various transaction types supported by the USB module. The transactions are portrayed as error free. The effect of errors in the data flow are discussed later.
ENDPOINT 0 TRANSACTIONS: Control Write SETUP DATA0 ACK OUT DATA1 ACK
OUT
DATA0
ACK
OUT
DATA0/1
ACK
IN Control Read SETUP DATA0 ACK IN DATA1
DATA1
ACK
ACK
IN
DATA0
ACK
IN
DATA0/1
ACK
OUT No-Data Control SETUP DATA0 ACK IN DATA1
DATA1
ACK
ACK
ENDPOINTS 1 & 2 TRANSACTIONS: KEY: Interrupt IN DATA0/1 ACK Unrelated Bus Traffic Host Generated Device Generated
Bulk Transmit IN DATA0/1 ACK
Figure 9-3. Supported Transaction Types Per Endpoint
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 103
Universal Serial Bus Module (USB)
Each USB transaction is comprised of a series of packets. The USB module supports the packet types shown in Figure 9-4. Token packets are generated by the USB host and decoded by the USB device. Data and handshake packets are both decoded and generated by the USB device, depending on the type of transaction.
Token Packet: IN OUT SETUP Data Packet: DATA0 DATA1 Handshake Packet: ACK NAK STALL SYNC PID PID EOP SYNC PID PID DATA 0 - 8 Bytes CRC16 EOP SYNC PID PID ADDR ENDP CRC5 EOP
Figure 9-4. Supported USB Packet Types The following sections detail each segment used to form a complete USB transaction. 9.5.1.1 Sync Pattern The NRZI bit pattern shown in Figure 9-5 is used as a synchronization pattern and is prefixed to each packet. This pattern is equivalent to a data pattern of seven 0s followed by a 1 ($80).
SYNC PATTERN NRZI Data Encoding Idle PID0 PID1
Figure 9-5. Sync Pattern
Technical Data 104 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) Functional Description
The start of a packet (SOP) is signaled by the originating port by driving the D+ and D- lines from the idle state (also referred to as the J state) to the opposite logic level (also referred to as the K state). This switch in levels represents the first bit of the sync field. Figure 9-6 shows the data signaling and voltage levels for the start of packet and the sync pattern.
VOH (min.)
VSE (max) VSE (min.) VOL (min.) VSS FIRST BIT OF PACKET BUS IDLE SOP END OF SYNC
Figure 9-6. SOP, Sync Signaling, and Voltage Levels 9.5.1.2 Packet Identifier Field The packet identifier field is an 8-bit number comprised of the 4-bit packet identification and its complement. The field follows the sync pattern and determines the direction and type of transaction on the bus. Table 9-2 shows the packet identifier values for the supported packet types. Table 9-2. Supported Packet Identifiers
Packet Identifier Value %1001 %0001 %1101 %0011 %1011 %0010 %1010 %1110 Packet Identifier Type IN Token OUT Token SETUP Token DATA0 Packet DATA1 Packet ACK Handshake NAK Handshake STALL Handshake
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 105
Universal Serial Bus Module (USB)
9.5.1.3 Address Field (ADDR) The address field is a 7-bit number that is used to select a particular USB device. This field is compared to the lower seven bits of the UADDR register to determine if a given transaction is targeting the MCU USB device. 9.5.1.4 Endpoint Field (ENDP) The endpoint field is a 4-bit number that is used to select a particular endpoint within a USB device. For the MCU, this will be a binary number between 0 and 2 inclusive. Any other value will cause the transaction to be ignored. 9.5.1.5 Cyclic Redundancy Check (CRC) Cyclic redundancy checks are used to verify the address and data stream of a USB transaction. This field is five bits wide for token packets and 16 bits wide for data packets. CRCs are generated in the transmitter and sent on the USB data lines after both the endpoint field and the data field. 9.5.1.6 End-of-Packet (EOP) The single-ended 0 (SE0) state is used to signal an end-of-packet (EOP). The single-ended 0 state is indicated by both D+ and D- being below 0.8V. EOP will be signaled by driving D+ and D- to the single-ended 0 state for two bit times followed by driving the lines to the idle state for one bit time. The transition from the single-ended 0 to the idle state defines the end of the packet. The idle state is asserted for one bit time and then both the D+ and D- output drivers are placed in their high-impedance state. The bus termination resistors hold the bus in the idle state. Figure 9-7 shows the data signaling and voltage levels for an end-of-packet transaction.
Technical Data 106 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) Functional Description
LAST BIT OF PACKET EOP STROBE VOH (min.)
BUS DRIVEN TO IDLE STATE BUS FLOATS BUS IDLE
VSE (max) VSE (min.) VOL (min.) VSS
Figure 9-7. EOP Transaction Voltage Levels The width of the SE0 in the EOP is about two bit times. The EOP width is measured with the same capacitive load used for maximum rise and fall times and is measured at the same level as the differential signal crossover points of the data lines.
tPeriod DATA CROSSOVER LEVEL
DIFFERENTIAL DATA LINES
EOP WIDTH
Figure 9-8. EOP Width Timing
9.5.2 Reset Signaling The USB module will detect a reset signaled on the bus by the presence of an extended SE0 at the USB data pins of a device. The MCU seeing a single-ended 0 on its USB data inputs for more than 8s treats that signal as a reset. A USB sourced reset will hold the MCU in reset for the duration of the reset on the USB bus. The USB bit in the reset status register (RSR) will be set after the internal reset is removed. Refer to 8.8.1 Reset Status Register for more detail. The MCU's reset recovery sequence is detailed in Section 8. System Integration Module (SIM).
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB) Technical Data 107
Universal Serial Bus Module (USB)
The reset flag bit (RSTF) in the USB interrupt register 1 (UIR1) also will be set after the internal reset is removed. Refer to 9.8.3 USB Interrupt Register 1 for more detail. After a reset is removed, the device will be in the default, but not yet addressed or configured state (refer to Section 9.1 USB Device States of the Universal Serial Bus Specification Rev. 1.1). The device must be able to accept a device address via a SET_ADDRESS command (refer to Section 9.4 Standard Device Request in the Universal Serial Bus Specification Rev. 1.1) no later than 10ms after the reset is removed. Reset can wake a device from the suspended mode.
NOTE:
USB Reset can be configured not to generate a reset signal to the CPU by setting the URSTD bit of the configuration register (see Section 5. Configuration Register (CONFIG)). When a USB reset is detected, the CPU generates an USB interrupt.
9.5.3 Suspend The MCU supports suspend mode for low power. Suspend mode should be entered when the USB data lines are in the idle state for more than 3ms. Entry into suspend mode is controlled by the SUSPND bit in the USB interrupt register. Any low-speed bus activity should keep the device out of the suspend state. Low-speed devices are kept awake by periodic low-speed EOP signals from the host. This is referred to as low speed keep alive (refer to Section 11.8.4.1 Low-Speed Keep-alive in the Universal Serial Bus Specification Rev. 1.1). Firmware should monitor the EOPF flag and enter suspend mode by setting the SUSPND bit if an EOP is not detected for 3ms. Per the USB specification, the bus powered USB system is required to draw less than 500A from the VDD supply when in the suspend state. This includes the current supplied by the voltage regulator to the 1.5k to ground termination resistors placed at the host end of the USB bus. This low-current requirement means that firmware is responsible for entering stop mode once the USB module has been placed in the suspend state.
Technical Data 108 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) Functional Description
9.5.4 Resume After Suspend The MCU can be activated from the suspend state by normal bus activity, a USB reset signal, or by a forced resume driven from the MCU. 9.5.4.1 Host Initiated Resume The host signals resume by initiating resume signalling (K state) for at least 20ms followed by a standard low-speed EOP signal. This 20ms ensures that all devices in the USB network are awakened. After resuming the bus, the host must begin sending bus traffic within 3ms to prevent the device from re-entering suspend mode. 9.5.4.2 USB Reset Signalling Reset can wake a device from the suspended mode. 9.5.4.3 Remote Wakeup The MCU also supports the remote wakeup feature. The firmware has the ability to exit suspend mode by signaling a resume state to the upstream host or hub. A non-idle state (K state) on the USB data lines is accomplished by asserting the FRESUM bit in the UCR1 register. When using the remote wakeup capability, the firmware must wait for at least 5ms after the bus is in the idle state before sending the remote wakeup resume signaling. This allows the upstream devices to get into their suspend state and prepare for propagating resume signaling. The FRESUM bit should be asserted to cause the resume state on the USB data lines for at least 10ms, but not more than 15ms. Note that the resume signalling is controlled by the FRESUM bit and meeting the timing specifications is dependent on the firmware. When FRESUM is cleared by firmware, the data lines will return to their high-impedance state. Refer to the register definitions (see 9.8.6 USB Control Register 1) for more information about how the force resume (FRESUM) bit can be used to initiate the remote wakeup feature.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 109
Universal Serial Bus Module (USB)
9.5.5 Low-Speed Device Low-speed devices are configured by the position of a pull-up resistor on the USB D- pin of the MCU. Low-speed devices are terminated as shown in Figure 9-9 with the pull-up on the D- line.
VREG (3.3V)
MCU
1.5 k D+ USB LOW-SPEED CABLE D-
Figure 9-9. External Low-Speed Device Configuration For low-speed transmissions, the transmitter's EOP width must be between 1.25s and 1.50s. These ranges include timing variations due to differential buffer delay and rise/fall time mismatches and to noise and other random effects. A low-speed receiver must accept a 670ns SE0 followed by a J transition as a valid EOP. An SE0 shorter than 330ns or an SE0 not followed by a J transition are rejected as an EOP. Any SE0 that is 8s or longer is automatically a reset.
9.6 Clock Requirements
The low-speed data rate is nominally 1.5Mbps. The OSCXCLK signal driven by the oscillator circuits is the clock source for the USB module and requires that a 6-MHz oscillator circuit be connected to the OSC1 and OSC2 pins. The permitted frequency tolerance for low-speed functions is approximately 1.5% (15,000 ppm). This tolerance includes inaccuracies from all sources: initial frequency accuracy, crystal capacitive loading, supply voltage on the oscillator, temperature, and aging. The jitter in the low-speed data rate must be less than 10ns.
Technical Data 110 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) Hardware Description
9.7 Hardware Description
The USB module as previously shown in Figure 9-2 contains three functional blocks: the low-speed USB transceiver, the USB control logic, and the USB registers. The following details the function of the regulator, transceiver, and control logic. See 9.8 I/O Registers for details of the register settings.
9.7.1 Voltage Regulator The USB data lines are required by the USB specification to have an output voltage between 2.8V and 3.6V. The data lines also are required to have an external 1.5k pull-up resistor connected between a data line and a voltage source between 3.0V and 3.6V. Figure 9-10 shows the worst case electrical connection for the voltage regulator.
4.0V - 5.5V
3.3V REGULATOR R1 LOW-SPEED TRANSCEIVER D+
USB DATA LINES
USB CABLE D- R1 = 1.5k 5% R2 = 15k 5% R2 R2
HOST OR HUB
Figure 9-10. Regulator Electrical Connections
9.7.2 USB Transceiver The USB transceiver provides the physical interface to the USB D+ and D- data lines. The transceiver is composed of two parts: an output drive circuit and a receiver.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 111
Universal Serial Bus Module (USB)
9.7.2.1 Output Driver Characteristics The USB transceiver uses a differential output driver to drive the USB data signal onto the USB cable. The static output swing of the driver in its low state is below the VOL of 0.3V with a 1.5k load to 3.6V and in its high state is above the VOH of 2.8V with a 15k load to ground. The output swings between the differential high and low state are well balanced to minimize signal skew. Slew rate control on the driver is used to minimize the radiated noise and cross talk. The driver's outputs support 3-state operation to achieve bidirectional half duplex operation. The driver can tolerate a voltage on the signal pins of -1.0V to 5.5V with respect to local ground reference without damage. 9.7.2.2 Low Speed (1.5 Mbps) Driver Characteristics The rise and fall time of the signals on this cable are greater than 75ns and less than 300ns. The edges are matched to within 20% to minimize RFI emissions and signal skew. USB data transmission is done with differential signals. A differential input receiver is used to accept the USB data signal. A differential 1 on the bus is represented by D+ being at least 200mV more positive than D- as seen at the receiver, and a differential 0 is represented by D- being at least 200mV more positive than D+ as seen at the receiver. The signal cross over point must be between 1.3V and 2.0V.
ONE BIT TIME (1.5 Mb/s)
VSE (max) VSE (min.) VSS
SIGNAL PINS PASS OUTPUT SPEC LEVELS WITH MINIMAL REFLECTIONS AND RINGING
Figure 9-11. Receiver Characteristics
Technical Data 112 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) Hardware Description
The receiver features an input sensitivity of 200mV when both differential data inputs are in the differential common mode range of 0.8V to 2.5V as shown in Figure 9-12. In addition to the differential receiver, there is a single-ended receiver (schmitt trigger) for each of the two data lines.
Differential Input voltage Range Differential Output Crossover Voltage Range
-1.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
5.5
INPUT VOLTAGE RANGE (VOLTS)
Figure 9-12. Differential Input Sensitivity Range 9.7.2.3 Receiver Data Jitter The data receivers for all types of devices must be able to properly decode the differential data in the presence of jitter. The more of the bit time that any data edge can occupy and still be decoded, the more reliable the data transfer will be. Data receivers are required to decode differential data transitions that occur in a window plus and minus a nominal quarter bit time from the nominal (centered) data edge position. Jitter will be caused by the delay mismatches and by mismatches in the source and destination data rates (frequencies). The receive data jitter budget for low speed is given in Section 16. Electrical Specifications. The specification includes the consecutive (next) and paired transition values for each source of jitter. 9.7.2.4 Data Source Jitter The source of data can have some variation (jitter) in the timing of edges of the data transmitted. The time between any set of data transitions is NxTPeriod jitter time, where N is the number of bits between the transitions and TPeriod is defined as the actual period of the data rate. The data jitter is measured with the same capacitive load used for maximum rise and fall times and is measured at the crossover points of the data lines as shown in Figure 9-13.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB) Technical Data 113
Universal Serial Bus Module (USB)
tPeriod DIFFERENTIAL DATA LINES CROSSOVER POINTS
JITTER
CONSECUTIVE TRANSITIONS
PAIRED TRANSITIONS
Figure 9-13. Data Jitter For low-speed transmissions, the jitter time for any consecutive differential data transitions must be within 25ns and within 10ns for any set of paired differential data transitions. These jitter numbers include timing variations due to differential buffer delay, rise/fall time mismatches, internal clock source jitter, noise and other random effects. 9.7.2.5 Data Signal Rise and Fall Time The output rise time and fall time are measured between 10% and 90% of the signal. Edge transition time for the rising and falling edges of low-speed signals is 75ns (minimum) into a capacitive load (CL) of 200pF and 300ns (maximum) into a capacitive load of 600pF. The rising and falling edges should be transitioning (monotonic) smoothly when driving the cable to avoid excessive EMI.
RISE TIME
+
FALL TIME 90% 90%
CL
DIFFERENTIAL DATA LINES 10% 10% tR tF
+
CL
LOW SPEED: 75ns at CL = 200pF, 300ns at CL = 600 pF
Figure 9-14. Data Signal Rise and Fall Time
Technical Data 114 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) I/O Registers
9.7.3 USB Control Logic The USB control logic manages data movement between the CPU and the transceiver. The control logic handles both transmit and receive operations on the USB. It contains the logic used to manipulate the transceiver and the endpoint registers. The byte count buffer is loaded with the active transmit endpoints byte count value during transmit operations. This same buffer is used for receive transactions to count the number of bytes received and, upon the end of the transaction, transfer that number to the receive endpoints byte count register. When transmitting, the control logic handles parallel-to-serial conversion, CRC generation, NRZI encoding, and bit stuffing. When receiving, the control logic handles sync detection, packet identification, end-of-packet detection, bit (un)stuffing, NRZI decoding, CRC validation, and serial-to-parallel conversion. Errors detected by the control logic include bad CRC, timeout while waiting for EOP, and bit stuffing violations.
9.8 I/O Registers
These I/O registers control and monitor USB operation: * * * * * * * USB address register (UADDR) USB control registers 0-4 (UCR0-UCR4) USB status registers 0-1 (USR0-USR1) USB interrupt registers 0-2 (UIR0-UIR2) USB endpoint 0 data registers 0-7 (UE0D0-UE0D7) USB endpoint 1 data registers 0-7 (UE1D0-UE1D7) USB endpoint 2 data registers 0-7 (UE2D0-UE2D7)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 115
Universal Serial Bus Module (USB)
9.8.1 USB Address Register
Address: $0038 Bit 7 Read: USBEN Write: Reset: 0* 0 0 0 0 0 0 0 UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 6 5 4 3 2 1 Bit 0
* USBEN bit is reset by POR or LVI reset only.
Figure 9-15. USB Address Register (UADDR) USBEN -- USB Module Enable This read/write bit enables and disables the USB module and the USB pins. When USBEN is set, the USB module is enabled and the PTE4 interrupt is disabled. When USBEN is clear, the USB module will not respond to any tokens, USB reset and USB related interrupts are disabled, and pins PTE4/D- and PTE3/D+ function as high current open-drain I/O port pins PTE4 and PTE3. 1 = USB function enabled and PTE4 interrupt is disabled 0 = USB function disabled including USB interrupt, reset and reset interrupt UADD[6:0] -- USB Function Address These bits specify the USB address of the device. Reset clears these bits.
Technical Data 116 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) I/O Registers
9.8.2 USB Interrupt Register 0
Address: $0039 Bit 7 Read: EOPIE Write: Reset: 0 0 0 0 0 0 0 0 SUSPND TXD2IE 6 5 4 0 TXD1IE 3 2 0 TXD0IE RXD0IE 1 Bit 0
= Unimplemented
Figure 9-16. USB Interrupt Register 0 (UIR0) EOPIE -- End-of-Packet Detect Interrupt Enable This read/write bit enables the USB to generate CPU interrupt requests when the EOPF bit becomes set. Reset clears the EOPIE bit. 1 = End-of-packet sequence detection can generate a CPU interrupt request 0 = End-of-packet sequence detection cannot generate a CPU interrupt request SUSPND -- USB Suspend Bit To save power, this read/write bit should be set by the software if a 3-ms constant idle state is detected on the USB bus. Setting this bit puts the transceiver into a power-saving mode. The RESUMF flag must be cleared before setting SUSPND. Software must clear this bit after the resume flag (RESUMF) is set while this resume interrupt flag is serviced. TXD2IE -- Endpoint 2 Transmit Interrupt Enable This read/write bit enables the transmit endpoint 2 to generate CPU interrupt requests when the TXD2F bit becomes set. Reset clears the TXD2IE bit. 1 = Transmit endpoint 2 can generate a CPU interrupt request 0 = Transmit endpoint 2 cannot generate a CPU interrupt request
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 117
Universal Serial Bus Module (USB)
TXD1IE -- Endpoint 1 Transmit Interrupt Enable This read/write bit enables the transmit endpoint 1 to generate CPU interrupt requests when the TXD1F bit becomes set. Reset clears the TXD1IE bit. 1 = Transmit endpoints 1 can generate a CPU interrupt request 0 = Transmit endpoints 1 cannot generate a CPU interrupt request TXD0IE -- Endpoint 0 Transmit Interrupt Enable This read/write bit enables the transmit endpoint 0 to generate CPU interrupt requests when the TXD0F bit becomes set. Reset clears the TXD0IE bit. 1 = Transmit endpoint 0 can generate a CPU interrupt request 0 = Transmit endpoint 0 cannot generate a CPU interrupt request RXD0IE -- Endpoint 0 Receive Interrupt Enable This read/write bit enables the receive endpoint 0 to generate CPU interrupt requests when the RXD0F bit becomes set. Reset clears the RXD0IE bit. 1 = Receive endpoint 0 can generate a CPU interrupt request 0 = Receive endpoint 0 cannot generate a CPU interrupt request 9.8.3 USB Interrupt Register 1
Address: $003A Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 EOPF 6 RSTF 5 TXD2F 4 0 3 TXD1F 2 RESUMF 1 TXD0F Bit 0 RXD0F
= Unimplemented
Figure 9-17. USB Interrupt Register 1 (UIR1) EOPF -- End-of-Packet Detect Flag This read-only bit is set when a valid end-of-packet sequence is detected on the D+ and D- lines. Software must clear this flag by writing a logic 1 to the EOPFR bit. Reset clears this bit. Writing to EOPF has no effect. 1 = End-of-packet sequence has been detected 0 = End-of-packet sequence has not been detected
Technical Data 118 Universal Serial Bus Module (USB) MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) I/O Registers
RSTF -- USB Reset Flag This read-only bit is set when a valid reset signal state is detected on the D+ and D- lines. If the URSTD bit of the configuration register (CONFIG) is clear, this reset detection will generate an internal reset signal to reset the CPU and other peripherals including the USB module. If the URSTD bit is set, this reset detection will generate an USB interrupt. This bit is cleared by writing a logic 1 to the RSTFR bit. This bit also is cleared by a POR reset.
NOTE:
The USB bit in the RSR register (see 8.8.1 Reset Status Register) is also a USB reset indicator. TXD2F -- Endpoint 2 Data Transmit Flag This read-only bit is set after the data stored in endpoint 2 transmit buffers has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the TXD2FR bit. To enable the next data packet transmission, TX2E also must be set. If the TXD2F bit is not cleared, a NAK handshake will be returned in the next IN transaction. Reset clears this bit. Writing to TXD2F has no effect. 1 = Transmit on endpoint 2 has occurred 0 = Transmit on endpoint 2 has not occurred TXD1F -- Endpoint 1 Data Transmit Flag This read-only bit is set after the data stored in the endpoint 1 transmit buffer has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the TXD1FR bit. To enable the next data packet transmission, TX1E also must be set. If the TXD1F bit is not cleared, a NAK handshake will be returned in the next IN transaction. Reset clears this bit. Writing to TXD1F has no effect. 1 = Transmit on endpoint 1has occurred 0 = Transmit on endpoint 1has not occurred
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 119
Universal Serial Bus Module (USB)
RESUMF -- Resume Flag This read-only bit is set when USB bus activity is detected while the SUSPND bit is set. Software must clear this flag by writing a logic 1 to the RESUMFR bit. Reset clears this bit. Writing a logic 0 to RESUMF has no effect. 1 = USB bus activity has been detected 0 = No USB bus activity has been detected TXD0F -- Endpoint 0 Data Transmit Flag This read-only bit is set after the data stored in endpoint 0 transmit buffers has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the TXD0FR bit. To enable the next data packet transmission, TX0E also must be set. If the TXD0F bit is not cleared, a NAK handshake will be returned in the next IN transaction. Reset clears this bit. Writing to TXD0F has no effect. 1 = Transmit on endpoint 0 has occurred 0 = Transmit on endpoint 0 has not occurred RXD0F -- Endpoint 0 Data Receive Flag This read-only bit is set after the USB module has received a data packet and responded with an ACK handshake packet. Software must clear this flag by writing a logic 1 to the RXD0FR bit after all of the received data has been read. Software also must set the RX0E bit to 1 to enable the next data packet reception. If the RXD0F bit is not cleared, the USB will respond with a NAK handshake to any endpoint 0 OUT tokens; but does not respond to a SETUP token. Reset clears this bit. Writing to RXD0F has no effect. 1 = Receive on endpoint 0 has occurred 0 = Receive on endpoint 0 has not occurred
Technical Data 120 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) I/O Registers
9.8.4 USB Interrupt Register 2
Address: $0018 Bit 7 Read: Write: Reset: 0 EOPFR 0 6 0 RSTFR 0 5 0 TXD2FR 0 0 4 0 3 0 2 0 1 0 Bit 0 0 RXD0FR 0
TXD1FR RESUMFR TXD0FR 0 0 0
Figure 9-18. USB Interrupt Register 2 (UIR2) EOPFR -- End-of-Packet Flag Reset Writing a logic 1 to this write-only bit will clear the EOPF bit if it is set. Writing a logic 0 to the EOPFR has no effect. Reset clears this bit. RSTFR -- Clear Reset Indicator Bit Writing a logic 1 to this write-only bit will clear the RSTF bit if it is set. Writing a logic 0 to the RSTFR has no effect. Reset clears this bit. TXD2FR -- Endpoint 2 Transmit Flag Reset Writing a logic 1 to this write-only bit will clear the TXD2F bit if it is set. Writing a logic 0 to TXD2FR has no effect. Reset clears this bit. TXD1FR -- Endpoint 1 Transmit Flag Reset Writing a logic 1 to this write-only bit will clear the TXD1F bit if it is set. Writing a logic 0 to TXD1FR has no effect. Reset clears this bit. RESUMFR -- Resume Flag Reset Writing a logic 1 to this write-only bit will clear the RESUMF bit if it is set. Writing to RESUMFR has no effect. Reset clears this bit. TXD0FR -- Endpoint 0 Transmit Flag Reset Writing a logic 1 to this write-only bit will clear the TXD0F bit if it is set. Writing a logic 0 to TXD0FR has no effect. Reset clears this bit. RXD0FR -- Endpoint 0 Receive Flag Reset Writing a logic 1 to this write-only bit will clear the RXD0F bit if it is set. Writing a logic 0 to RXD0FR has no effect. Reset clears this bit.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 121
Universal Serial Bus Module (USB)
9.8.5 USB Control Register 0
Address: $003B Bit 7 Read: T0SEQ Write: Reset: 0 0 0 0 0 0 0 0 6 0 TX0E RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 5 4 3 2 1 Bit 0
Figure 9-19. USB Control Register 0 (UCR0) T0SEQ -- Endpoint 0 Transmit Sequence Bit This read/write bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction directed at endpoint 0. Toggling of this bit must be controlled by software. Reset clears this bit. 1 = DATA1 token active for next endpoint 0 transmit 0 = DATA0 token active for next endpoint 0 transmit TX0E -- Endpoint 0 Transmit Enable This read/write bit enables a transmit to occur when the USB host controller sends an IN token to endpoint 0. Software should set this bit when data is ready to be transmitted. It must be cleared by software when no more endpoint 0 data needs to be transmitted. If this bit is 0 or the TXD0F is set, the USB will respond with a NAK handshake to any endpoint 0 IN tokens. Reset clears this bit. 1 = Data is ready to be sent 0 = Data is not ready. Respond with NAK RX0E -- Endpoint 0 Receive Enable This read/write bit enables a receive to occur when the USB host controller sends an OUT token to endpoint 0. Software should set this bit when data is ready to be received. It must be cleared by software when data cannot be received. If this bit is 0 or the RXD0F is set, the USB will respond with a NAK handshake to any endpoint 0 OUT tokens; but does not respond to a SETUP token. Reset clears this bit. 1 = Data is ready to be received 0 = Not ready for data. Respond with NAK
Technical Data 122 Universal Serial Bus Module (USB) MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) I/O Registers
TP0SIZ3-TP0SIZ0 -- Endpoint 0 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for endpoint 0. These bits are cleared by reset.
9.8.6 USB Control Register 1
Address: $003C Bit 7 Read: T1SEQ Write: Reset: 0 0 0 0 0 0 0 0 STALL1 TX1E FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 6 5 4 3 2 1 Bit 0
Figure 9-20. USB Control Register 1 (UCR1) T1SEQ -- Endpoint 1 Transmit Sequence Bit This read/write bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction directed to endpoint 1. Toggling of this bit must be controlled by software. Reset clears this bit. 1 = DATA1 token active for next endpoint 1 transmit 0 = DATA0 token active for next endpoint 1 transmit STALL1 -- Endpoint 1 Force Stall Bit This read/write bit causes endpoint 1 to return a STALL handshake when polled by either an IN or OUT token by the USB host controller. Reset clears this bit. 1 = Send STALL handshake 0 = Default TX1E -- Endpoint 1 Transmit Enable This read/write bit enables a transmit to occur when the USB host controller sends an IN token to endpoint 1. The appropriate endpoint enable bit, ENABLE1 bit in the UCR3 register, also should be set. Software should set the TX1E bit when data is ready to be transmitted. It must be cleared by software when no more data needs to be transmitted.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 123
Universal Serial Bus Module (USB)
If this bit is 0 or the TXD1F is set, the USB will respond with a NAK handshake to any endpoint 1 directed IN tokens. Reset clears this bit. 1 = Data is ready to be sent 0 = Data is not ready. Respond with NAK FRESUM -- Force Resume This read/write bit forces a resume state (K or non-idle state) onto the USB data lines to initiate a remote wakeup. Software should control the timing of the forced resume to be between 10 and 15 ms. Setting this bit will not cause the RESUMF bit to be set. 1 = Force data lines to K state 0 = Default TP1SIZ3-TP1SIZ0 -- Endpoint 1 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for endpoint 1. These bits are cleared by reset.
9.8.7 USB Control Register 2
Address: $0019 Bit 7 Read: T2SEQ Write: Reset: 0 0 0 0 0 0 0 0 STALL2 TX2E 6 5 4 0 TP2SIZ3 TP2SIZ2 TP2SIZ1 TP2SIZ0 3 2 1 Bit 0
Figure 9-21. USB Control Register 2 (UCR2) T2SEQ -- Endpoint 2 Transmit Sequence Bit This read/write bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction directed to endpoint 2. Toggling of this bit must be controlled by software. Reset clears this bit. 1 = DATA1 token active for next endpoint 2 transmit 0 = DATA0 token active for next endpoint 2 transmit
Technical Data 124 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) I/O Registers
STALL2 -- Endpoint 2 Force Stall Bit This read/write bit causes endpoint 2 to return a STALL handshake when polled by either an IN or OUT token by the USB host controller. Reset clears this bit. 1 = Send STALL handshake 0 = Default TX2E -- Endpoint 2 Transmit Enable This read/write bit enables a transmit to occur when the USB host controller sends an IN token to endpoint 2. The appropriate endpoint enable bit, ENABLE2 bit in the UCR3 register, also should be set. Software should set the TX2E bit when data is ready to be transmitted. It must be cleared by software when no more data needs to be transmitted. If this bit is 0 or the TXD2F is set, the USB will respond with a NAK handshake to any endpoint 2 directed IN tokens. Reset clears this bit. 1 = Data is ready to be sent 0 = Data is not ready. Respond with NAK TP2SIZ3-TP2SIZ0 -- Endpoint 2 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for endpoint 2. These bits are cleared by reset.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 125
Universal Serial Bus Module (USB)
9.8.8 USB Control Register 3
Address: $001A Bit 7 Read: Write: Reset: 0 TX1ST 6 0 OSTALL0 ISTALL0 TX1STR 0 0 0 0 0* 0 0 5 4 3 0 PULLEN ENABLE2 ENABLE1 2 1 Bit 0
= Unimplemented * PULLEN bit is reset by POR or LVI reset only.
Figure 9-22. USB Control Register 3 (UCR3) TX1ST -- Endpoint 0 Transmit First Flag This read-only bit is set if the endpoint 0 data transmit flag (TXD0F) is set when the USB control logic is setting the endpoint 0 data receive flag (RXD0F). In other words, if an unserviced endpoint 0 transmit flag is still set at the end of an endpoint 0 reception, then this bit will be set. This bit lets the firmware know that the endpoint 0 transmission happened before the endpoint 0 reception. Reset clears this bit. 1 = IN transaction occurred before SETUP/OUT 0 = IN transaction occurred after SETUP/OUT TX1STR -- Clear Endpoint 0 Transmit First Flag Writing a logic 1 to this write-only bit will clear the TX1ST bit if it is set. Writing a logic 0 to the TX1STR has no effect. Reset clears this bit. OSTALL0 -- Endpoint 0 Force STALL Bit for OUT token This read/write bit causes endpoint 0 to return a STALL handshake when polled by an OUT token by the USB host controller. The USB hardware clears this bit when a SETUP token is received. Reset clears this bit. 1 = Send STALL handshake 0 = Default
Technical Data 126 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) I/O Registers
ISTALL0 -- Endpoint 0 Force STALL Bit for IN token This read/write bit causes endpoint 0 to return a STALL handshake when polled by an IN token by the USB host controller. The USB hardware clears this bit when a SETUP token is received. Reset clears this bit. 1 = Send STALL handshake 0 = Default PULLEN -- Pull-up Enable This read/write bit controls the pull-up option for the USB D- pin if the USB module is enabled. 1 = Configure D- pin to have internal pull-up 0 = Disconnect D- pin internal pull-up ENABLE2 -- Endpoint 2 Enable This read/write bit enables endpoint 2 and allows the USB to respond to IN packets addressed to endpoint 2. Reset clears this bit. 1 = Endpoint 2 is enabled and can respond to an IN token 0 = Endpoint 2 is disabled ENABLE1 -- Endpoint 1 Enable This read/write bit enables endpoint 1 and allows the USB to respond to IN packets addressed to endpoint 1. Reset clears this bit. 1 = Endpoint 1 is enabled and can respond to an IN token 0 = Endpoint 1 is disabled
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 127
Universal Serial Bus Module (USB)
9.8.9 USB Control Register 4 USB control register 4 directly controls the USB data pins D+ and D-. If the FUSBO bit, and the USBEN bit of the USB address register (UADDR) are set, the output buffers of the USB modules are enabled and the corresponding levels of the USB data pins D+ and D- are equal to the values set by the FDP and the FDM bits.
Address: $001B Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 FUSBO FDP FDM 2 1 Bit 0
= Unimplemented
Figure 9-23. USB Control Register 4 (UCR4) FUSBO -- Force USB Output This read/write bit enables the USB output buffers. 1 = Enables USB output buffers 0 = USB module in normal operation FDP -- Force D+ This read/write bit determinates the output level of D+. 1 = D+ at output high level 0 = D+ at output low level FDM -- Force D- This read/write bit determinates the output level of D-. 1 = D- at output high level 0 = D- at output low level
NOTE:
Customers must be very careful when setting the UCR4 register. When the FUSBO and the USBEN bits are set, the USB module is in output mode and it will not recognize any USB signals including the USB reset signal. The UCR4 register is used for some special applications. Customers are not normally expected to use this register.
Technical Data 128 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) I/O Registers
9.8.10 USB Status Register 0
Address: $003D Bit 7 Read: Write: Reset: = Unimplemented Unaffected by reset R0SEQ 6 SETUP 5 0 4 0 3 RP0SIZ3 2 RP0SIZ2 1 RP0SIZ1 Bit 0 RP0SIZ0
Figure 9-24. USB Status Register 0 (USR0) R0SEQ -- Endpoint 0 Receive Sequence Bit This read-only bit indicates the type of data packet last received for endpoint 0 (DATA0 or DATA1). 1 = DATA1 token received in last endpoint 0 receive 0 = DATA0 token received in last endpoint 0 receive SETUP -- SETUP Token Detect Bit This read-only bit indicates that a valid SETUP token has been received. 1 = Last token received for endpoint 0 was a SETUP token 0 = Last token received for endpoint 0 was not a SETUP token RP0SIZ3-RP0SIZ0 -- Endpoint 0 Receive Data Packet Size These read-only bits store the number of data bytes received for the last OUT or SETUP transaction for endpoint 0.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 129
Universal Serial Bus Module (USB)
9.8.11 USB Status Register 1
Address: $003E Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 TXACK 5 TXNAK 4 TXSTL 3 0 2 0 1 0 Bit 0 0
= Unimplemented
U = Unaffected by reset
Figure 9-25. USB Status Register 2 (USR1) TXACK -- ACK Token Transmit Bit This read-only bit indicates that an ACK token has been transmitted. This bit is updated at the end of the data transmission. 1 = Last token transmitted for endpoint 0 was an ACK token 0 = Last token transmitted for endpoint 0 was not an ACK token TXNAK -- NAK Token Transmit Bit This read-only bit indicates that a TXNAK token has been transmitted. This bit is updated at the end of the data transmission. 1 = Last token transmitted for endpoint 0 was a NAK token 0 = Last token transmitted for endpoint 0 was not a NAK token TXSTL -- STALL Token Transmit Bit This read-only bit indicates that a STALL token has been transmitted. This bit is updated at the end of the data transmission. 1 = Last token transmitted for endpoint 0 was a STALL token 0 = Last token transmitted for endpoint 0 was not a STALL token
Technical Data 130 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) I/O Registers
9.8.12 USB Endpoint 0 Data Registers
Address: $0020 Bit 7 Read: UE0R07 Write: UE0T07 Reset: UE0D0 6 UE0R06 UE0T06 5 UE0R05 UE0T05 4 UE0R04 UE0T04 3 UE0R03 UE0T03 2 UE0R02 UE0T02 1 UE0R01 UE0T01 Bit 0 UE0R00 UE0T00
Unaffected by reset
Address: $0027 UE0D7 UE0R76 UE0T76 UE0R75 UE0T75 UE0R74 UE0T74 UE0R73 UE0T73 UE0R72 UE0T72 UE0R71 UE0T71 Read: UE0R77 Write: UE0T77 Reset:
UE0R70 UE0T70
Unaffected by reset
Figure 9-26. USB Endpoint 0 Data Register (UE0D0-UE0D7) UE0Rx7-UE0Rx0 -- Endpoint 0 Receive Data Buffer These read-only bits are serially loaded with OUT token or SETUP token data directed at endpoint 0. The data is received over the USB's D+ and D- pins. UE0Tx7-UE0Tx0 -- Endpoint 0 Transmit Data Buffer These write-only buffers are loaded by software with data to be sent on the USB bus on the next IN token directed at endpoint 0.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 131
Universal Serial Bus Module (USB)
9.8.13 USB Endpoint 1 Data Registers
Address: $0028 Bit 7 Read: Write: UE1T07 Reset: UE1T06 UE1T05 UE1T04 UE1T03 UE1T02 UE1T01 UE1T00 UE1D0 6 5 4 3 2 1 Bit 0
Unaffected by reset
Address: Read: Write: UE1T77 Reset: = Unimplemented UE1T76 UE1T75 UE1T74 UE1T73 UE1T72 UE1T71 $002F UE1D7
UE1T70
Unaffected by reset
Figure 9-27. USB Endpoint 1 Data Register (UE1D0-UE1D7) UE1Tx7-UE1Tx0 -- Endpoint 1 Transmit or Receive Data Buffer These write-only buffers are loaded by software with data to be sent on the USB bus on the next IN token directed at endpoint 1.
Technical Data 132 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) I/O Registers
9.8.14 USB Endpoint 2 Data Registers
Address: $0030 Bit 7 Read: Write: UE2T07 Reset: UE2T06 UE2T05 UE2T04 UE2T03 UE2T02 UE2T01 UE2T00 UE2D0 6 5 4 3 2 1 Bit 0
Unaffected by reset
Address: Read: Write: UE2T77 Reset: UE2T76 UE2T75 UE2T74 UE2T73 UE2T72 UE2T71 $0037 UE2D7
UE2T70
Unaffected by reset
Figure 9-28. USB Endpoint 2 Data Register (UE2D0-UE2D7) UE2Tx7-UE2Tx0 -- Endpoint 2 Transmit Data Buffer These write-only buffers are loaded by software with data to be sent on the USB bus on the next IN token directed at endpoint 2.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 133
Universal Serial Bus Module (USB) 9.9 USB Interrupts
The USB module is capable of generating interrupts and causing the CPU to execute the USB interrupt service routine. There are three types of USB interrupts: * * * End-of-transaction interrupts signify either a completed transaction receive or transmit transaction. Resume interrupts signify that the USB bus is reactivated after having been suspended. End-of-packet interrupts signify that a low-speed end-of-packet signal was detected.
All USB interrupts share the same interrupt vector. Firmware is responsible for determining which interrupt is active.
9.9.1 USB End-of-Transaction Interrupt There are four possible end-of-transaction interrupts: * * Endpoint 0 receive Endpoint 0, 1 or 2 transmit
End-of-transaction interrupts occur as detailed in the following sections.
Technical Data 134 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) USB Interrupts
9.9.1.1 Receive Control Endpoint 0 For a control OUT transaction directed at endpoint 0, the USB module will generate an interrupt by setting the RXD0F flag in the UIR0 register. The conditions necessary for the interrupt to occur are shown in the flowchart in Figure 9-29.
VALID OUT TOKEN RECEIVED FOR ENDPOINT 0 Y VALID DATA TOKEN RECEIVED FOR ENDPOINT 0? Y USB MODULE ENABLED? (USBEN = 1) Y ENDPOINT 0 RECEIVE NOT STALLED? (OSTALL0 = 0) Y ENDPOINT 0 RECEIVE READY TO RECEIVE? (RX0E = 1) AND (RXD0F = 0) Y ACCEPT DATA SET/CLEAR R0SEQ BIT N SEND NAK HANDSHAKE N SEND STALL HANDSHAKE N NO RESPONSE FROM USB FUNCTION N TIMEOUT NO RESPONSE FROM USB FUNCTION
ERROR FREE DATA PACKET? Y SET RXD0F TO 1
N
IGNORE TRANSACTION NO RESPONSE FROM USB FUNCTION
RECEIVE CONTROL ENDPOINT INTERRUPT ENABLED? (RXD0IE = 1) Y VALID TRANSACTION INTERRUPT GENERATED
N
NO INTERRUPT
Figure 9-29. OUT Token Data Flow for Receive Endpoint 0
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 135
Universal Serial Bus Module (USB)
SETUP transactions cannot be stalled by the USB function. A SETUP received by a control endpoint will clear the ISTALL0 and OSTALL0 bits. The conditions for receiving a SETUP interrupt are shown in Figure 9-30.
VALID SETUP TOKEN RECEIVED FOR ENDPOINT 0? Y USB MODULE ENABLED? (USBEN = 1) Y ENDPOINT 0 RECEIVE READY TO RECEIVE? (RX0E = 1) AND (RXD0F = 0) Y N NO RESPONSE FROM USB FUNCTION N NO RESPONSE FROM USB FUNCTION
ACCEPT DATA SET/CLEAR R0SEQ BIT SET SETUP BIT TO 1
ERROR FREE DATA PACKET? Y SET RXD0F TO 1
N
IGNORE TRANSACTION NO RESPONSE FROM USB FUNCTION
RECEIVE CONTROL ENDPOINT INTERRUPT ENABLED? (RXD0IE = 1) Y VALID TRANSACTION INTERRUPT GENERATED
N
NO INTERRUPT
Figure 9-30. SETUP Token Data Flow for Receive Endpoint 0
Technical Data 136 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) USB Interrupts
9.9.1.2 Transmit Control Endpoint 0 For a control IN transaction directed at endpoint 0, the USB module will generate an interrupt by setting the TXD0F flag in the UIR1 register. The conditions necessary for the interrupt to occur are shown in the flowchart in Figure 9-31.
VALID IN TOKEN RECEIVED FOR ENDPOINT 0 Y USB MODULE ENABLED? (USBEN = 1) Y TRANSMIT ENDPOINT NOT STALLED BY FIRMWARE (ISTALL0 = 0)? Y TRANSMIT ENDPOINT READY TO TRANSFER? (TX0E = 1) AND (TXD0F = 0) Y SEND DATA DATA PID SET BY T0SEQ N SEND NAK HANDSHAKE N SEND STALL HANDSHAKE N NO RESPONSE FROM USB FUNCTION
ACK RECEIVED AND NO TIMEOUT CONDITION OCCURS? Y SET TXD0F TO 1
N
NO RESPONSE FROM USB FUNCTION
TRANSMIT ENDPOINT INTERRUPT ENABLED? (TXD0IE = 1) Y VALID TRANSACTION INTERRUPT GENERATED
N
NO INTERRUPT
Figure 9-31. IN Token Data Flow for Transmit Endpoint 0
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 137
Universal Serial Bus Module (USB)
9.9.1.3 Transmit Endpoint 1 For an IN transaction directed at endpoint 1, the USB module will generate an interrupt by setting the TXD1F in the UIR1 register. The conditions necessary for the interrupt to occur are shown in Figure 9-32.
VALID IN TOKEN RECEIVED FOR ENDPOINT 1 Y USB MODULE ENABLED? (USBEN = 1) Y TRANSMIT ENDPOINT NOT STALLED BY FIRMWARE (STALL1 = 1)? Y TRANSMIT ENDPOINT READY TO TRANSFER? (TX1E = 1) AND (TXD1F = 0) AND (UE1TR = 0) Y TRANSMIT ENDPOINT ENABLED? (ENABLE = 1) Y SEND DATA DATA PID SET BY T1SEQ N NO RESPONSE FROM USB FUNCTION N SEND NAK HANDSHAKE N SEND STALL HANDSHAKE N NO RESPONSE FROM USB FUNCTION
ACK RECEIVED AND NO TIMEOUT CONDITION OCCURS? Y SET TXD1F TO 1
N
NO RESPONSE FROM USB FUNCTION
TRANSMIT ENDPOINT INTERRUPT ENABLED? (TXD1IE = 1) Y VALID TRANSACTION INTERRUPT GENERATED
N
NO INTERRUPT
Figure 9-32. IN Token Data Flow for Transmit Endpoint 1
Technical Data 138 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Universal Serial Bus Module (USB) USB Interrupts
9.9.1.4 Transmit Endpoint 2 For an IN transaction directed at endpoint 2, the USB module will generate an interrupt by setting the TXD2F in the UIR1 register.
9.9.2 Resume Interrupt The USB module will generate a CPU interrupt if low-speed bus activity is detected after entering the suspend state. A transition of the USB data lines to the non-idle state (K state) while in the suspend mode will set the RESUMF flag in the UIR1 register. There is no interrupt enable bit for this interrupt source and an interrupt will be executed if the I bit in the CCR is cleared. A resume interrupt can only occur while the MCU is in the suspend mode.
9.9.3 End-of-Packet Interrupt The USB module can generate a USB interrupt upon detection of an end-of-packet signal for low-speed devices. Upon detection of an end-of-packet signal, the USB module sets the EOPF bit and will generate a CPU interrupt if the EOPIE bit in the UIR0 register is set.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Universal Serial Bus Module (USB)
Technical Data 139
Universal Serial Bus Module (USB)
Technical Data 140 Universal Serial Bus Module (USB)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Technical Data -- MC68HC08JB1
Section 10. Timer Interface Module (TIM)
10.1 Contents
10.2 10.3 10.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.5.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . 146 10.5.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . 147 10.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . 147 10.5.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . 148 10.5.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . 149 10.5.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
10.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 10.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.8.1 TIM Clock Pin (PTE0/TCLK) . . . . . . . . . . . . . . . . . . . . . . . 153 10.8.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1) . . . . . . . 153 10.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 10.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . 154 10.9.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 10.9.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . 157 10.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . .158 10.9.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM) Technical Data 141
Timer Interface Module (TIM) 10.2 Introduction
This section describes the timer interface module (TIM2, Version B). The TIM is a 2-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 10-1 is a block diagram of the TIM.
NOTE:
TCH1 and TCLK pins are not available on this timer.
10.3 Features
Features of the TIM include: * input capture/output compare channel - Rising-edge, falling-edge, or any-edge input capture trigger - Set, clear, or toggle output compare action Buffered and unbuffered pulse width modulation (PWM) signal generation Programmable TIM clock input - 7-frequency internal bus clock prescaler selection * * * Free-running or modulo up-count operation Toggle any channel pin on overflow TIM counter stop and reset bits
* *
10.4 Pin Name Conventions
The TIM share three I/O pins with three port E I/O pins. The full name of the TIM I/O pin is listed in Table 10-1. The generic pin name appear in the text that follows. Table 10-1. TIM Pin Name Conventions
TIM Generic Pin Names: Full TIM Pin Names: TCLK Not available TCH0 PTE1/TCH0 TCH1 Not available
Technical Data 142 Timer Interface Module (TIM)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Timer Interface Module (TIM) Functional Description
10.5 Functional Description
Figure 10-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence. The two TIM channels are programmable independently as input capture or output compare channels.
TCLK (Not available) PRESCALER SELECT INTERNAL BUS CLOCK TSTOP TRST 16-BIT COUNTER PRESCALER
PS2
PS1
PS0
TOF TOIE
INTERRUPT LOGIC
16-BIT COMPARATOR TMODH:TMODL TOV0 CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH MS0A MS0B TOV1 INTERNAL BUS CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MS1A CH1IE CH1F INTERRUPT LOGIC ELS1B ELS1A CH1MAX PORT LOGIC TCH1 (Not available) CH0IE CH0F INTERRUPT LOGIC ELS0B ELS0A CH0MAX PORT LOGIC TCH0
Figure 10-1. TIM Block Diagram
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
Technical Data 143
Timer Interface Module (TIM)
Addr.
Register Name TIM Status and Control Register (TSC) Read: Write: Reset: Read:
Bit 7 TOF
6 TOIE
5 TSTOP
4 0 TRST
3 0
2 PS2
1 PS1 0 Bit9
Bit 0 PS0 0 Bit8
$000A
0 0 Bit15 0 Bit14 1 Bit13
0 Bit12
0 Bit11
0 Bit10
$000C
TIM Counter Register High (TCNTH)
Write: Reset: Read: 0 Bit7 0 Bit6 0 Bit5 0 Bit4 0 Bit3 0 Bit2 0 Bit1 0 Bit0
$000D
TIM Counter Register Low (TCNTL)
Write: Reset: 0 Bit15 Write: Reset: Read: Bit7 Write: Reset: Read: Write: Reset: Read: Bit15 Write: Reset: Read: Bit7 Write: Reset: Read: Write: Reset: CH1F CH1IE 0 0 0 0 0 0 0 0 0 0 MS1A ELS1B ELS1A TOV1
CH1MAX
0 Bit14 1 Bit6 1 CH0IE
0 Bit13 1 Bit5 1 MS0B 0 Bit13
0 Bit12 1 Bit4 1 MS0A 0 Bit12
0 Bit11 1 Bit3 1 ELS0B 0 Bit11
0 Bit10 1 Bit2 1 ELS0A 0 Bit10
0 Bit9 1 Bit1 1 TOV0 0 Bit9
0 Bit8 1 Bit0 1
CH0MAX
$000E
TIM Counter Modulo Register High (TMODH)
Read:
1
$000F
TIM Counter Modulo Register Low (TMODL)
1 CH0F 0 0
$0010
TIM Channel 0 Status and Control Register (TSC0)
0 Bit14
0 Bit8
$0011
TIM Channel 0 Register High (TCH0H)
Indeterminate after reset Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
$0012
TIM Channel 0 Register Low (TCH0L)
Indeterminate after reset
$0013
TIM Channel 1 Status and Control Register (TSC1)
= Unimplemented
Figure 10-2. TIM I/O Register Summary
Technical Data 144 Timer Interface Module (TIM)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Timer Interface Module (TIM) Functional Description
$0014
TIM Channel 1 Register High (TCH1H)
Read: Bit15 Write: Reset: Read: Bit7 Write: Reset: = Unimplemented Indeterminate after reset Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Indeterminate after reset Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
$0015
TIM Channel 1 Register Low (TCH1L)
Figure 10-2. TIM I/O Register Summary 10.5.1 TIM Counter Prescaler The TIM clock source can be one of the seven prescaler outputs or the TIM clock pin, PTE0/TCLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register (TSC) select the TIM clock source.
10.5.2 Input Capture With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests.
10.5.3 Output Compare With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
Technical Data 145
Timer Interface Module (TIM)
10.5.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 10.5.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: * When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. When changing to a larger output compare value, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period.
*
Technical Data 146 Timer Interface Module (TIM)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Timer Interface Module (TIM) Functional Description
10.5.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the PTE1/TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the PTE1/TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, PTE2/TCH1, is available as a general-purpose I/O pin.
NOTE:
In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares.
10.5.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 10-3 shows, the output compare value in the TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to set the pin if the state of the PWM pulse is logic 0.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
Technical Data 147
Timer Interface Module (TIM)
OVERFLOW PERIOD OVERFLOW OVERFLOW
PULSE WIDTH PTEx/TCHxA
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 10-3. PWM Period and Pulse Width The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is 000 (see 10.9.1 TIM Status and Control Register). The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%. 10.5.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 10.5.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written.
Technical Data 148 Timer Interface Module (TIM) MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Timer Interface Module (TIM) Functional Description
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: * When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period.
*
NOTE:
In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.
10.5.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the PTE1/TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The TIM channel 0 registers initially control the pulse width on the PTE1/TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, PTE2/TCH1, is available as a general-purpose I/O pin.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
Technical Data 149
Timer Interface Module (TIM)
NOTE:
In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals.
10.5.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use this initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width. 4. In TIM channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. (See Table 10-3.) b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. (See Table 10-3.)
NOTE:
In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to selfcorrect in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
Technical Data 150 Timer Interface Module (TIM)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Timer Interface Module (TIM) Interrupts
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. (See 10.9.4 TIM Channel Status and Control Registers.)
10.6 Interrupts
The following TIM sources can generate interrupt requests: * TIM overflow flag (TOF) -- The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register. TIM channel flags (CH1F:CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE = 1. CHxF and CHxIE are in the TIM channel x status and control register.
*
10.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low powerconsumption standby modes.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
Technical Data 151
Timer Interface Module (TIM)
10.7.1 Wait Mode The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction.
10.7.2 Stop Mode The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt.
10.8 I/O Signals
Port E shares three of its pins with the TIM. PTE0/TCLK is an external clock input to the TIM prescaler. The two TIM channel I/O pins are PTE1/TCH0 and PTE2/TCH1.
Technical Data 152 Timer Interface Module (TIM)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Timer Interface Module (TIM) I/O Registers
10.8.1 TIM Clock Pin (PTE0/TCLK) PTE0/TCLK is an external clock input that can be the clock source for the TIM counter instead of the prescaled internal bus clock. Select the PTE0/TCLK input by writing logic 1s to the three prescaler select bits, PS[2:0]. (See 10.9.1 TIM Status and Control Register.) The minimum TCLK pulse width, TCLKLMIN or TCLKHMIN, is: 1 ------------------------------------ + t SU bus frequency The maximum TCLK frequency is: bus frequency / 2 PTE0/TCLK is available as a general-purpose I/O pin when not used as the TIM clock input. When the PTE0/TCLK pin is the TIM clock input, it is an input regardless of the state of the DDRE0 bit in data direction register E.
10.8.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1) Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTE1/TCH0 can be configured as buffered output compare or buffered PWM pins.
10.9 I/O Registers
The following I/O registers control and monitor operation of the TIM: * * * * * TIM status and control register (TSC) TIM counter registers (TCNTH:TCNTL) TIM counter modulo registers (TMODH:TMODL) TIM channel status and control registers (TSC0 and TSC1) TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
Technical Data 153
Timer Interface Module (TIM)
10.9.1 TIM Status and Control Register The TIM status and control register: * * * * *
Address:
Enables TIM overflow interrupts Flags TIM overflows Stops the TIM counter Resets the TIM counter Prescales the TIM counter clock
$000A Bit 7 6 TOIE 5 TSTOP TRST 0 1 0 0 0 0 0 4 0 3 0 PS2 PS1 PS0 2 1 Bit 0
Read: Write: Reset:
TOF 0 0
= Unimplemented
Figure 10-4. TIM Status and Control Register (TSC) TOF -- TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect. 1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value TOIE -- TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled
Technical Data 154 Timer Interface Module (TIM) MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Timer Interface Module (TIM) I/O Registers
TSTOP -- TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active
NOTE:
Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. TRST -- TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as logic 0. Reset clears the TRST bit. 1 = Prescaler and TIM counter cleared 0 = No effect
NOTE:
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000. PS[2:0] -- Prescaler Select Bits These read/write bits select either the PTE0/TCLK pin or one of the seven prescaler outputs as the input to the TIM counter as Table 10-2 shows. Reset clears the PS[2:0] bits. Table 10-2. Prescaler Selection
PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 TIM Clock Source Internal Bus Clock /1 Internal Bus Clock / 2 Internal Bus Clock / 4 Internal Bus Clock / 8 Internal Bus Clock / 16 Internal Bus Clock / 32 Internal Bus Clock / 64 PTE0/TCLK
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
Technical Data 155
Timer Interface Module (TIM)
10.9.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers.
NOTE:
If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break.
TCNTH Address: $000C Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 Bit 15 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8
TCNTL
Address: $000D Bit 7 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0
Read: Write: Reset:
Bit 7
0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-5. TIM Counter Registers (TCNTH:TCNTL)
Technical Data 156 Timer Interface Module (TIM)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Timer Interface Module (TIM) I/O Registers
10.9.3 TIM Counter Modulo Registers The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
TMODH Address: $000E Bit 7 Read: Bit 15 Write: Reset: 1 1 1 1 1 1 1 1 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 6 5 4 3 2 1 Bit 0
TMODL
Address: $000F Bit 7 6 Bit 6 1 5 Bit 5 1 4 Bit 4 1 3 Bit 3 1 2 Bit 2 1 1 Bit 1 1 Bit 0 Bit 0 1
Read: Bit 7 Write: Reset: 1
Figure 10-6. TIM Counter Modulo Registers (TMODH:TMODL)
NOTE:
Reset the TIM counter before writing to the TIM counter modulo registers.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
Technical Data 157
Timer Interface Module (TIM)
10.9.4 TIM Channel Status and Control Registers Each of the TIM channel status and control registers does the following: * * * * * * * *
TSC0
Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture, output compare, or PWM operation Selects high, low, or toggling output on output compare Selects rising edge, falling edge, or any edge as the active input capture trigger Selects output toggling on TIM overflow Selects 0% and 100% PWM duty cycle Selects buffered or unbuffered output compare/PWM operation
Address: $0010 Bit 7 6 CH0IE 5 MS0B 0 4 MS0A 0 3 ELS0B 0 2 ELS0A 0 1 TOV0 0 Bit 0 CH0MAX 0
Read: Write: Reset:
CH0F 0 0 0
TSC1
Address: $0013 Bit 7 6 CH1IE 5 0 MS1A 0 0 ELS1B 0 ELS1A 0 TOV1 0 CH1MAX 0 4 3 2 1 Bit 0
Read: Write: Reset:
CH1F 0 0 0
= Unimplemented
Figure 10-7. TIM Channel Status and Control Registers (TSC0:TSC1)
Technical Data 158 Timer Interface Module (TIM)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Timer Interface Module (TIM) I/O Registers
CHxF -- Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading the TIM channel x status and control register with CHxF set and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE -- Channel x Interrupt Enable Bit This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB -- Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM channel 0 status and control register. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA -- Mode Select Bit A When ELSxB:ELSxA 0:0, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 10-3. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
Technical Data 159
Timer Interface Module (TIM)
When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. (See Table 10-3.). Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). ELSxB and ELSxA -- Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to port E, and pin PTEx/TCHx is available as a general-purpose I/O pin. Table 10-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. Table 10-3. Mode, Edge, and Level Selection
MSxB X X 0 0 0 0 0 0 1 1 1 MSxA 0 1 0 0 0 1 1 1 X X X ELSxB ELSxA 0 0 0 1 1 0 1 1 0 1 1 0 0 1 0 1 1 0 1 1 0 1 Output Compare or PWM Input Capture Mode Output Preset Configuration Pin under port control; initial output level high Pin under port control; initial output level low Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Toggle output on compare Clear output on compare Set output on compare
Buffered Toggle output on compare Output Clear output on compare Compare or Buffered Set output on compare PWM
Technical Data 160 Timer Interface Module (TIM)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Timer Interface Module (TIM) I/O Registers
NOTE:
Before enabling a TIM channel register for input capture operation, make sure that the PTEx/TCHx pin is stable for at least two bus clocks. TOVx -- Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIM counter overflow 0 = Channel x pin does not toggle on TIM counter overflow
NOTE:
When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time. CHxMAX -- Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 10-8 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW PERIOD PTEx/TCHx OVERFLOW OVERFLOW OVERFLOW OVERFLOW
OUTPUT COMPARE CHxMAX
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 10-8. CHxMAX Latency
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Timer Interface Module (TIM)
Technical Data 161
Timer Interface Module (TIM)
10.9.5 TIM Channel Registers These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written.
TCH0H Address: Bit 7 Read: Write: Reset: TCH0L Address: Bit 7 Read: Write: Reset: TCH1H Address: Bit 7 Read: Write: Reset: TCH1L Address: Bit 7 Read: Write: Reset: Bit 7 $0015 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0 Bit 15 $0014 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8 Bit 7 $0012 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0 Bit 15 $0011 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Figure 10-9. TIM Channel Registers (TCH0H/L:TCH1H/L)
Technical Data 162 Timer Interface Module (TIM)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Technical Data -- MC68HC08JB1
Section 11. Input/Output Ports (I/O)
11.1 Contents
11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
11.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 11.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 11.3.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.4 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.4.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.4.2 Data Direction Register C. . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.5 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.5.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.5.2 Data Direction Register D. . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.6 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.6.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 11.6.2 Data Direction Register E. . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.7 Port Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 11.7.1 Port Option Control Register . . . . . . . . . . . . . . . . . . . . . . . 177
11.2 Introduction
Thirteen (13) bidirectional input-output (I/O) pins form four parallel ports. All I/O pins are programmable as inputs or outputs.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Input/Output Ports (I/O)
Technical Data 163
Input/Output Ports (I/O)
NOTE:
Connect any unused I/O pins to an appropriate logic level, either VREG or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage.
Bit 7 PTA7 6 PTA6 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0
Addr.
Register Name Read: Port A Data Register Write: (PTA) Reset: Read: Port C Data Register Write: (PTC) Reset: Read: Port D Data Register Write: (PTD) Reset:
$0000
Unaffected by reset 0 0 0 0 0 0 0 PTC0
$0002
Unaffected by reset 0 0 0 0 0 0 PTD1 PTD0
$0003
Unaffected by reset DDRA6 0 DDRA5 0 DDRA4 0 DDRA3 0 DDRA2 0 DDRA1 0 DDRA0 0
Read: DDRA7 Data Direction Register A $0004 Write: (DDRA) Reset: 0* * DDRA7 bit is reset by POR or LVI reset only. Read: Data Direction Register C $0006 Write: (DDRC) Reset: Read: Data Direction Register D $0007 Write: (DDRD) Reset: Read: Port E Data Register Write: (PTE) Reset: 0
0
0
0
0
0
0
DDRC0 0 DDRD0 0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 DDRD1 0 PTE1
0 0
0 0
0 0
0 PTE4
0 PTE3
0 0
$0008
Unaffected by reset 0 0 0 DDRE4 0 PTE4P 0 DDRE3 0 PTE3P 0 0 DDRE1 0 0 0
Read: Data Direction Register E $0009 Write: (DDRE) Reset:
0
0 0
0 PTDILDD 0
0 PCP 0
0 PAP 0
$001D
Read: Port Option Control PTE20P Register Write: (POCR) Reset: 0
0
0
= Unimplemented
Figure 11-1. I/O Port Register Summary
Technical Data 164 Input/Output Ports (I/O) MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Input/Output Ports (I/O) Introduction
Table 11-1. Port Control Register Bits Summary
Module Control Port Bit
0 1 2 3 A 4 5 6 7 C 0 DDRA4 DDRA5 DDRA6 DDRA7 DDRC0 -- --
DDR Module
DDRA0 DDRA1 DDRA2 DDRA3 KBI KBIER ($0017) KBIE4 KBIE5 KBIE6 KBIE7 --
Pin Register Control Bit
KBIE0 KBIE1 KBIE2 KBIE3 PTA0/KBA0 PTA1/KBA1 PTA2/KBA2 PTA3/KBA3 PTA4/KBA4 PTA5/KBA5 PTA6/KBA6 PTA7/KBA7 PTC0
D
0-1 1
DDRD[0:1] DDRE1 DDRE3
--
-- TSC0 ($0010) UADDR ($0038)
-- ELS0B:ELS0A USBEN
PTD0/1 PTE1/TCH0 PTE3/D+
TIM
USB
E
3 4
DDRE4
PTE4/D-
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Input/Output Ports (I/O)
Technical Data 165
Input/Output Ports (I/O) 11.3 Port A
Port A is an 8-bit general-purpose bidirectional I/O port with software configurable pullups, and it shares its pins with the keyboard interrupt module (KBI).
11.3.1 Port A Data Register The port A data register contains a data latch for each of the eight port A pins.
Address: $0000 Bit 7 Read: PTA7 Write: Reset:
Alternative
6 PTA6
5 PTA5
4 PTA4
3 PTA3
2 PTA2
1 PTA1
Bit 0 PTA0
Unaffected by reset KBA7 KBA6 Optional pullup KBA5 Optional pullup KBA4 Optional pullup KBA3 Optional pullup KBA2 Optional pullup KBA1 Optional pullup KBA0 Optional pullup
Function:
Additional Optional Function: pullup
Figure 11-2. Port A Data Register (PTA) PTA[7:0] -- Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. The port A pullup enable bit, PAP, in the port option control register (POCR) enables pullups on port A pins if the respective pin is configured as an input. (See 11.7 Port Options.) KBA7-KBA0 -- Keyboard Interrupts The keyboard interrupt enable bits, KBIE7-KBIE0, in the keyboard interrupt enable register (KBIER), enable the port A pins as external interrupt pins. (See Section 13. Keyboard Interrupt Module (KBI).)
Technical Data 166 Input/Output Ports (I/O)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Input/Output Ports (I/O) Port A
11.3.2 Data Direction Register A Data direction register A determines whether each port A pin is an input or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer.
Address: $0004 Bit 7 Read: DDRA7 Write: Reset: 0* 0 0 0 0 0 0 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 6 5 4 3 2 1 Bit 0
* DDRA7 bit is reset by POR or LVI reset only.
Figure 11-3. Data Direction Register A (DDRA) DDRA[7:0] -- Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[7:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 11-4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004) INTERNAL DATA BUS RESET WRITE PTA ($0000) PTAx PTAx DDRAx
READ PTA ($0000)
Figure 11-4. Port A I/O Circuit
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Input/Output Ports (I/O) Technical Data 167
Input/Output Ports (I/O)
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 11-2 summarizes the operation of the port A pins. Table 11-2. Port A Pin Functions
DDRA Bit 0 1 PTA Bit I/O Pin Mode Accesses to DDRA Read/Write X(1) X Input, Hi-Z(2) Output DDRA[7:0] DDRA[7:0] Accesses to PTA Read Pin PTA[7:0] Write PTA[7:0](3) PTA[7:0]
NOTES: 1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect input.
11.4 Port C
Port C is an 1-bit general-purpose bidirectional I/O port with software configurable pullup and current drive options.
11.4.1 Port C Data Register The port C data register contains a data latch for the PTC0 pin.
Address: $0002 Bit 7 Read: Write: Reset: Additional Function: Unaffected by reset Optional pullup 0 6 0 5 0 4 0 3 0 2 0 1 0 PTC0 Bit 0
Figure 11-5. Port C Data Register (PTC)
Technical Data 168 Input/Output Ports (I/O)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Input/Output Ports (I/O) Port C
PTC0 -- Port C Data Bit-0 This read/write bit is software-programmable. Data direction is under the control of the DDRC0 bit in data direction register C. Reset has no effect on PTC0 data. The port C pullup enable bit, PCP, in the port option control register (POCR) enables the pullup on PTC0 if the pin is configured as an input. (See 11.7 Port Options.)
11.4.2 Data Direction Register C Data direction register C determines whether PTC0 pin is an input or an output. Writing a logic 1 to DDRC0 bit enables the output buffer for the PTC0 pin; a logic 0 disables the output buffer.
Address: $0006 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 DDRC0 Bit 0
Figure 11-6. Data Direction Register C (DDRC) DDRC0 -- Data Direction Register C Bit-0 This read/write bit control PTC0 data direction. Reset clears DDRC0, configuring PTC0 pin as an input. 1 = PTC0 pin configured as output 0 = PTC0 pin configured as input
NOTE:
Avoid glitches on PTC0 pin by writing to the port C data register before changing DDRC0 bit from 0 to 1. Figure 11-7 shows the port C I/O logic.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Input/Output Ports (I/O)
Technical Data 169
Input/Output Ports (I/O)
READ DDRC ($0006)
WRITE DDRC ($0006) INTERNAL DATA BUS RESET WRITE PTC ($0002) PTC0 PTC0 DDRC0
READ PTC ($0002)
Figure 11-7. Port C I/O Circuit When bit DDRC0 is a logic 1, reading address $0002 reads the PTC0 data latch. When bit DDRC0 is a logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 11-3 summarizes the operation of the PTC0 pin. Table 11-3. Port C Pin Functions
DDRC Bit 0 1 PTC Bit I/O Pin Mode Accesses to DDRC Read/Write PTC0 PTC0 Input, Hi-Z(1) Output DDRC0 DDRC0 Accesses to PTC Read Pin PTC0 Write PTC0(2) PTC0
NOTES: 1. Hi-Z = high impedance 2. Writing affects data register, but does not affect input.
11.5 Port D
Port D is an 1-bit general-purpose bidirectional I/O port. PTD1 and PTD0 internal pads are bonded together to form PTD0/1 pin. This pin is opendrain when configured as output, and can interface with 5V logic.
Technical Data 170 Input/Output Ports (I/O)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Input/Output Ports (I/O) Port D
11.5.1 Port D Data Register The port D data register contains a data latch for the PTD0/1 pin.
Address: $0003 Bit 7 Read: Write: Reset: Additional Function: Unaffected by reset
Open-drain Open-drain 25 mA sink 25mA sink
6 0
5 0
4 0
3 0
2 0
1 PTD1
Bit 0 PTD0
0
Figure 11-8. Port D Data Register (PTD) PTD[1:0] -- Port D Data Bit-1 and Bit-0 These two read/write bits are software programmable. Data direction of PTD0/1 pin is under control of these two data bits. Reset has no effect on port D data. Configure this register so that PTD1 = PTD0. The infrared LED drive bit, PTDILDD, in the port option control register (POCR) controls the drive options for the PTD0/1 pin. (See 11.7 Port Options.)
NOTE:
PTD1 and PTD0 internal pads are bonded together to PTD0/1 pin forming a 50mA high current drain pin. When both PTD1 and PTD0 are configured as output, the values of PTD0 and PTD1 should be written the same.
11.5.2 Data Direction Register D Data direction register D determines whether PTD0/1 pin is an input or an output. Writing a logic 1 to DDRD[1:0] bits enable the output buffer for the PTD0/1 pin; a logic 0 disables the output buffer.
Address: $0007 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 DDRD1 DDRD0 1 Bit 0
Figure 11-9. Data Direction Register D (DDRD)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Input/Output Ports (I/O) Technical Data 171
Input/Output Ports (I/O)
DDRD[1:0] -- Data Direction Register D Bit-1 and Bit-0 These two read/write bits control PTD0/1 pin data direction. Reset clears DDRD[1:0], configuring PTD0/1 pin as an input. Configure this register so that DDRD1 = DDRD0. 1 = PTD0/1 pin configured as output 0 = PTD0/1 pin configured as input PTD0/1 pin is open-drain when configured as output.
NOTE:
Avoid glitches on PTD0/1 pin by writing to PTD[1:0] before changing DDRD[1:0] bits from 0 to 1. Figure 11-10 shows the port D I/O circuit logic.
READ DDRD ($0007)
WRITE DDRD ($0007) INTERNAL DATA BUS RESET WRITE PTD ($0003) PTD1/PTD0 PTD0/1 DDRD1/DDRD0
READ PTD ($0003)
Figure 11-10. Port D I/O Circuit When bit DDRD[1:0] is a logic 1, reading address $0003 reads the PTD0/1 data latch. When bit DDRD[1:0] is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 11-4 summarizes the operation of the port D pins. Table 11-4. Port D Pin Functions
DDRD Bit 0 1 PTD Bit I/O Pin Mode Accesses to DDRD Read/Write PTD[1:0] PTD[1:0] Input, Hi-Z(1) Output DDRD[1:0] DDRD[1:0] Accesses to PTD Read Pin PTD0/1 Write PTD[1:0](2) PTD[1:0]
NOTES: 1. Hi-Z = high impedance 2. Writing affects data register, but does not affect input.
Technical Data 172 Input/Output Ports (I/O)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Input/Output Ports (I/O) Port E
11.6 Port E
Port E is a 3-bit special function port that shares one of its pins with the timer interface module (TIM) and two of its pins with the USB data pins D+ and D-. PTE4 and PTE3 are open-drain when configured as output.
11.6.1 Port E Data Register The port E data register contains a data latch for each of the three port E pins.
Address: $0008 Bit 7 Read: Write: Reset:
Alternative
6 0
5 0
4 PTE4
3 PTE3
2 0
1 PTE1
Bit 0 0
0
Unaffected by reset D- Optional pullup External interrupt
Open-drain Open-drain
Function: Additional Function: Additional Function:
D+ Optional pullup
TCH0 Optional pullup
= Unimplemented
Figure 11-11. Port E Data Register (PTE) PTE4, PTE3, PTE1 -- Port E Data Bits PTE4, PTE3, and PTE1 are read/write, software-programmable bits. Data direction of each port E pin is under the control of the corresponding bit in data direction register E. The PTE4 and PTE3 pullup enable bits, PTE4P and PTE3P, in the port option control register (POCR) enable 5k pullups on PTE4 and PTE3 if the respective pin is configured as an input and the USB module is disabled. (See 11.7 Port Options.)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Input/Output Ports (I/O)
Technical Data 173
Input/Output Ports (I/O)
The PTE1 pullup enable bit, PTE20P, in the port option control register (POCR) enables pullup on PTE1, regardless of the pin is configured as an input or an output. (See 11.7 Port Options.) PTE4 pin functions as an external interrupt when PTE4IE=1 in the IRQ option control register (IOCR) and USBEN=0 in the USB address register (USB disabled). (See 12.9 IRQ Option Control Register.) D- and D+ -- USB Data Pins D- and D+ are the differential data lines used by the USB module. (See Section 9. Universal Serial Bus Module (USB).) The USB module enable bit, USBEN, in the USB address register (UADDR) controls the pin options for PTE4/D- and PTE3/D+. When the USB module is enabled, PTE4/D- and PTE3/D+ function as USB data pins D- and D+. When the USB module is disabled, PTE4/D- and PTE3/D+ function as 10mA open-drain pins for PS/2 clock and data use. The Pullup enable bit, PULLEN, in the USB control register 3 (UCR3) enables a 1.5k pullup on D- pin when the USB module is enabled. (See 9.8.8 USB Control Register 3.)
NOTE:
PTE4/D- pin has two programmable pullup resistors. One is used for PTE4 when the USB module is disabled and another is used for D- when the USB module is enabled. TCH0 -- Timer Channel 0 I/O Bits The PTE1/TCH0 pin is the TIM input capture/output compare pin. The edge/level select bits, ELS0B and ELS0A, determine whether the PTE1/TCH0 pin is timer channel I/O pin or general-purpose I/O pin. (See Section 10. Timer Interface Module (TIM).)
NOTE:
Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the TIM. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins.
Technical Data 174 Input/Output Ports (I/O)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Input/Output Ports (I/O) Port E
11.6.2 Data Direction Register E Data direction register E determines whether each port E pin is an input or an output. Writing a logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer.
Address: $0009 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 5 0 DDRE4 DDRE3 4 3 2 0 DDRE1 1 Bit 0 0
= Unimplemented
Figure 11-12. Data Direction Register E (DDRE) DDRE4, DDRE3, DDRE1 -- Data Direction Register E Bits These read/write bits control port E data direction. Reset clears DDRE4, DDRE3, and DDRE1, configuring all port E pins as inputs. 1 = Corresponding port E pin configured as output 0 = Corresponding port E pin configured as input
NOTE:
Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from 0 to 1. Figure 11-13 shows the port E I/O circuit logic.
READ DDRE ($000C)
WRITE DDRE ($000C) INTERNAL DATA BUS RESET WRITE PTE ($0008) PTEx PTEx DDREx
READ PTE ($0008)
Figure 11-13. Port E I/O Circuit
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Input/Output Ports (I/O)
Technical Data 175
Input/Output Ports (I/O)
When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 11-3 summarizes the operation of the port E pins. Table 11-5. Port E Pin Functions
DDRE Bit PTE Bit PTE4 PTE3 PTE1 PTE4 PTE3 PTE1 I/O Pin Mode Accesses to DDRE Read/Write 0
(1)
Accesses to PTE Read Pin PTE4 PTE3 PTE1 Write PTE4(2) PTE3 PTE1 PTE4 PTE3 PTE1
Input, Hi-Z
DDRE4 DDRE3 DDRE1 DDRE4 DDRE3 DDRE1
1
Output
NOTES: 1. Hi-Z = high impedance 2. Writing affects data register, but does not affect input.
Technical Data 176 Input/Output Ports (I/O)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Input/Output Ports (I/O) Port Options
11.7 Port Options
All pins of port A, port C, and port E have programmable pullup resistors. PTD0/1 has LED drive capability. Port pins PTE4 and PTE3 have 10mA high current drive capability. 11.7.1 Port Option Control Register The port option control register controls the pullup options for port A, C, and E pins. It also controls the drive configuration on port D.
Address: $001D Bit 7 Read: PTE20P Write: Reset:
0 0 0 0 0 0 0 0
6 0
5 PTDILDD
4 PTE4P
3 PTE3P
2 PCP
1 0
Bit 0 PAP
Figure 11-14. Port Option Control Register (POCR) PTE20P -- PTE1 pin Pullup Enable This read/write bit controls the pullup option for the PTE1 pin. When set, a pullup device is connected regardless whether the pin is configured as an input or an output. 1 = Configure PTE1 to have an internal pullup to VREG 0 = Disconnect PTE1 internal pullup PTDILDD -- Infrared LED Drive Control This read/write bit controls the output current capability of PTD0/1 pin. When set, the PTD0/1 pin has 50mA current sink capability. An infrared LED can be connected directly between the PTD0/1 and VDD. 1 = PTD0/1 configured for infrared LED drive capability; when the pin is set as an output, the pin is an open-drain pin with 50mA current sink capability 0 = PTD0/1 configured as a standard open-drain I/O port pin
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Input/Output Ports (I/O)
Technical Data 177
Input/Output Ports (I/O)
PTE4P -- Pin PTE4 Pullup Enable This read/write bit controls the pullup option for the PTE4 pin. When set, a pullup device is connected when the pin is configured as an input and the USB module is disabled. 1 = Configure PTE4 to have an internal pullup to VDD 0 = Disconnect PTE4 internal pullup
NOTE:
When the USB module is enabled, the pullup controlled by PTE4P is disconnected; PTE4/D- pin functions as D- which has a 1.5k programmable pull-up resistor. (See 9.8.8 USB Control Register 3.) The pullup controlled by PTE4P is a pullup to VDD, as oppose to VREG. PTE3P -- Pin PTE3 Pullup Enable This read/write bit controls the pullup option for the PTE3 pin. When set, a pullup device is connected when the pin is configured as an input and the USB module is disabled. 1 = Configure PTE3 to have an internal pullup to VDD 0 = Disconnect PTE3 internal pullup
NOTE:
The pullup controlled by PTE3P is a pullup to VDD, as oppose to VREG. PCP -- Port C Pullup Enable This read/write bit controls the pullup option for the PTC0 pin. When set, a pullup device is connected when the pin is configured as an input. 1 = Configure PTC0 to have an internal pullup to VREG 0 = Disconnect PTC0 internal pullup PAP -- Port A Pullup Enable This read/write bit controls the pullup option for the PTA7-PTA0 pins. When set, a pullup device is connected when a pin is configured as an input. 1 = Configure port A to have internal pullups to VREG 0 = Disconnect port A internal pullups
Technical Data 178 Input/Output Ports (I/O)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Technical Data -- MC68HC08JB1
Section 12. External Interrupt (IRQ)
12.1 Contents
12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 PTE4/D- Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .183 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 184 IRQ Option Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . 185
12.2 Introduction
The IRQ module provides two external interrupt inputs: one dedicated IRQ pin and one shared port pin, PTE4/D-.
12.3 Features
Features of the IRQ module include: * * * * * * *
MC68HC08JB1 -- Rev. 2.0 MOTOROLA External Interrupt (IRQ)
Two external interrupt pins, IRQ (5V) and PTE4/D- (5V) IRQ interrupt control bits Hysteresis buffer Programmable edge-only or edge and level interrupt sensitivity Automatic interrupt acknowledge Low leakage IRQ pin for external RC wake up input Selectable internal pullup resistor
Technical Data 179
External Interrupt (IRQ) 12.4 Functional Description
A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Figure 12-1 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of the following actions occurs: * * Vector fetch -- A vector fetch automatically generates an interrupt acknowledge signal that clears the IRQ latch. Software clear -- Software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (ISCR). Writing a logic 1 to the ACK bit clears the IRQ latch. Reset -- A reset automatically clears the interrupt latch.
*
The external interrupt pin is falling-edge-triggered and is softwareconfigurable to be either falling-edge or low-level-triggered. The MODE bit in the ISCR controls the triggering sensitivity of the IRQ pin. When the interrupt pin is edge-triggered only, the CPU interrupt request remains set until a vector fetch, software clear, or reset occurs. When the interrupt pin is both falling-edge and low-level-triggered, the CPU interrupt request remains set until both of the following occur: * * Vector fetch or software clear Return of the interrupt pin to logic one
The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. When set, the IMASK bit in the ISCR mask all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE:
The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. (See 8.6 Exception Control.)
Technical Data 180 External Interrupt (IRQ)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
External Interrupt (IRQ) Functional Description
INTERNAL ADDRESS BUS
ACK RESET VECTOR FETCH DECODER HIGH VOLTAGE DETECT TO MODE SELECT LOGIC TO CPU FOR BIL/BIH INSTRUCTIONS
VDD IRQPD
INTERNAL
PULLUP DEVICE
VREG D CLR Q SYNCHRONIZER
IRQF
IRQ
CK IRQ FF IMASK
IRQ INTERRUPT REQUEST
TO PTE4 PULLUP ENABLE CIRCUITRY
MODE
VREG D PTE4 CLR Q
READ IOCR PTE4IF
CK
PTE4IE
Figure 12-1. IRQ Module Block Diagram
Addr. $001C Register Name IRQ Option Control Register Read: (IOCR) Write: Reset: $001E IRQ Status and Control Register Read: (ISCR) Write: Reset: Bit 7 0 6 0 5 0 4 0 3 0 2 PTE4IF PTE4IE 0 0 0 0 0 0 0 0 0 IRQF 0 0 IMASK ACK 0 0 0 0 0 0 0 0 MODE 0 IRQPD 0 1 Bit 0
= Unimplemented
Figure 12-2. IRQ I/O Register Summary
MC68HC08JB1 -- Rev. 2.0 MOTOROLA External Interrupt (IRQ) Technical Data 181
External Interrupt (IRQ)
12.5 IRQ Pin
The IRQ pin has a low leakage for input voltages ranging from 0V to VDD; suitable for applications using RC discharge circuitry to wake up the MCU. A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and lowlevel-sensitive. With MODE set, both of the following actions must occur to clear IRQ: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK bit in the interrupt status and control register (ISCR). The ACK bit is useful in applications that poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK bit latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the vector address at locations $FFF8 and $FFF9. Return of the IRQ pin to logic one -- As long as the IRQ pin is at logic zero, IRQ remains active.
*
The vector fetch or software clear and the return of the IRQ pin to logic one may occur in any order. The interrupt request remains pending as long as the IRQ pin is at logic zero. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or software clear immediately clears the IRQ latch. The IRQF bit in the ISCR register can be used to check for pending interrupts. The IRQF bit is not affected by the IMASK bit, which makes it useful in applications where polling is preferred.
Technical Data 182 External Interrupt (IRQ) MC68HC08JB1 -- Rev. 2.0 MOTOROLA
External Interrupt (IRQ) PTE4/D- Pin
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
NOTE: NOTE:
When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. An internal pullup resistor to VDD is connected to IRQ pin; this can be disabled by setting the IRQPD bit in the IRQ option control register ($001C).
12.6 PTE4/D- Pin
The PTE4 pin is configured as an interrupt input to trigger the IRQ interrupt when the following conditions are satisfied: * * The USB module is disabled (USBEN = 0) PTE4 pin configured for external interrupt input (PTE4IE = 1)
Setting PTE4IE configures the PTE4 pin to an input pin with an internal pullup device. The PTE4 interrupt is "ORed" with the IRQ input to trigger the IRQ interrupt (see Figure 12-1 . IRQ Module Block Diagram). Therefore, the IRQ status and control register affects both the IRQ pin and the PTE pin. An interrupt on PTE4 also sets the PTE4 interrupt flag, PTE4IF, in the IRQ option control register (IOCR).
12.7 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during the break state. (See Section 8. System Integration Module (SIM).) To allow software to clear the IRQ latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latches during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ latch.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA External Interrupt (IRQ) Technical Data 183
External Interrupt (IRQ) 12.8 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. The ISCR has the following functions: * * * *
Address:
Shows the state of the IRQ flag Clears the IRQ latch Masks IRQ interrupt request Controls triggering sensitivity of the IRQ pin
$001E Bit 7 6 0 5 0 4 0 3 IRQF 2 0 IMASK MODE
0
1
Bit 0
Read: Write: Reset:
0
ACK
0 0 0 0 0 0 0
= Unimplemented
Figure 12-3. IRQ Status and Control Register (ISCR) IRQF -- IRQ Flag This read-only status bit is high when the IRQ interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending ACK -- IRQ Interrupt Request Acknowledge Bit Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always reads as logic 0. Reset clears ACK. IMASK -- IRQ Interrupt Mask Bit Writing a logic 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK. 1 = IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled MODE -- IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE. 1 = IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only
Technical Data 184 External Interrupt (IRQ) MC68HC08JB1 -- Rev. 2.0 MOTOROLA
External Interrupt (IRQ) IRQ Option Control Register
12.9 IRQ Option Control Register
The IRQ option control register controls and monitors the external interrupt function available on the PTE4 pin. It also disables/enables the pullup resistor on the IRQ pin. * * *
Address:
Controls pullup option on IRQ pin Enables PTE4 pin for external interrupts to IRQ Shows the state of the PTE4 interrupt flag
$001C Bit 7 6 0 5 0 4 0 3 0 2 PTE4IF PTE4IE IRQPD
0
1
Bit 0
Read: Write: Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-4. IRQ Option Control Register (IOCR) PTE4IF -- PTE4 Interrupt Flag This read-only status bit is high when a falling edge on PTE4 pin is detected. PTE4IF bit clears when the IOCR is read. 1 = Falling edge on PTE4 is detected and PTE4IE is set 0 = Falling edge on PTE4 is not detected or PTE4IE is clear PTE4IE -- PTE4 Interrupt Enable This read/write bit enables or disables the interrupt function on the PTE4 pin to trigger the IRQ interrupt. Setting the PTE4IE bit and clearing the USBEN bit in the USB address register configure the PTE4 pin for interrupt function to the IRQ interrupt. Setting PTE4IE also enables the internal pullup on PTE4 pin. 1 = PTE4 interrupt enabled; triggers IRQ interrupt 0 = PTE4 interrupt disabled IRQPD -- IRQ Pullup Disable This read/write bit controls the pull-up option for the IRQ pin. 1 = Internal pull-up is disconnected 0 = Internal pull-up is connected between IRQ pin and VDD
MC68HC08JB1 -- Rev. 2.0 MOTOROLA External Interrupt (IRQ) Technical Data 185
External Interrupt (IRQ)
Technical Data 186 External Interrupt (IRQ)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Technical Data -- MC68HC08JB1
Section 13. Keyboard Interrupt Module (KBI)
13.1 Contents
13.2 13.3 13.4 13.5 13.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
13.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 13.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 13.8 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .193
13.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 13.9.1 Keyboard Status and Control Register. . . . . . . . . . . . . . . . 193 13.9.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . 195
13.2 Introduction
The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are accessible via PTA0-PTA7 pins.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Keyboard Interrupt Module (KBI)
Technical Data 187
Keyboard Interrupt Module (KBI) 13.3 Features
Features of the keyboard interrupt module include: * * * * Eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask Hysteresis buffers Programmable edge-only or edge- and level-interrupt sensitivity Exit from low-power modes
13.4 Pin Name Conventions
The KBI share eight I/O pins with eight port A I/O pins. The full name of the I/O pins are listed in Table 13-1. The generic pin name appear in the text that follows. Table 13-1. KBI Pin Name Conventions
Full KBI Pin Names: PTA7/KBA7 PTA6/KBA6 PTA5/KBA5 PTA4/KBA4 PTA3/KBA3 PTA2/KBA2 PTA1/KBA1 PTA0/KBA0 KBI Generic Pin Names: KBA7 KBA6 KBA5 KBA4 KBA3 KBA2 KBA1 KBA0
Technical Data 188 Keyboard Interrupt Module (KBI)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Keyboard Interrupt Module (KBI) Pin Name Conventions
INTERNAL BUS
KBA0 VREG . KBIE0 TO PULLUP ENABLE . KBA7 . D CLR Q
ACKK RESET
VECTOR FETCH DECODER KEYF SYNCHRONIZER Keyboard Interrupt Request
CK
KEYBOARD INTERRUPT FF
IMASKK
MODEK KBIE7 TO PULLUP ENABLE
Figure 13-1. Keyboard Module Block Diagram
Table 13-2. I/O Register Summary
Addr. Register Name Bit 7 0 6 0 5 0 4 0 3 KEYF 2 0 IMASKK ACKK 0 KBIE7 0 0 KBIE6 0 0 KBIE5 0 0 KBIE4 0 0 KBIE3 0 0 KBIE2 0 0 KBIE1 0 0 KBIE0 0 MODEK 1 Bit 0
Read: Keyboard Status and Control $0016 Register Write: (KBSCR) Reset: Read: Keyboard Interrupt Enable Register Write: (KBIER) Reset:
$0017
= Unimplemented
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Keyboard Interrupt Module (KBI)
Technical Data 189
Keyboard Interrupt Module (KBI) 13.5 Functional Description
Writing to the KBIE7-KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin also enables its internal pullup device. A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. * If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. If the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low.
*
NOTE:
To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. If the MODEK bit is set, the keyboard interrupt pins are both falling edgeand low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register (KBSCR). The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine also can prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFF0 and $FFF1.
Technical Data 190 Keyboard Interrupt Module (KBI)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Keyboard Interrupt Module (KBI) Keyboard Initialization
*
Return of all enabled keyboard interrupt pins to logic 1 -- As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set.
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling-edgesensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register.
NOTE:
Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin.
13.6 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the pullup device to reach a logic 1. Therefore, a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register. 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Keyboard Interrupt Module (KBI) Technical Data 191
Keyboard Interrupt Module (KBI)
3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in data direction register A. 2. Write logic 1s to the appropriate port A data register bits. 3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
13.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
13.7.1 Wait Mode The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode.
13.7.2 Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode.
Technical Data 192 Keyboard Interrupt Module (KBI)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Keyboard Interrupt Module (KBI) Keyboard Module During Break Interrupts
13.8 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. (See 13.9.1 Keyboard Status and Control Register.)
13.9 I/O Registers
These registers control and monitor operation of the keyboard module: * * Keyboard status and control register (KBSCR) Keyboard interrupt enable register (KBIER)
13.9.1 Keyboard Status and Control Register The keyboard status and control register: * * * * Flags keyboard interrupt requests Acknowledges keyboard interrupt requests Masks keyboard interrupt requests Controls keyboard interrupt triggering sensitivity
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Keyboard Interrupt Module (KBI)
Technical Data 193
Keyboard Interrupt Module (KBI)
Address:
$0016 Bit 7 6 0 5 0 4 0 3 KEYF 2 0 IMASKK MODEK 0 ACKK 0 0 0 0 0 0 0 1 Bit 0
Read: Write: Reset:
0
= Unimplemented
Figure 13-2. Keyboard Status and Control Register (KBSCR) Bits 7-4 -- Not used These read-only bits always read as logic 0s. KEYF -- Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending ACKK -- Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as logic 0. Reset clears ACKK. IMASKK -- Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK -- Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only
Technical Data 194 Keyboard Interrupt Module (KBI)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Keyboard Interrupt Module (KBI) I/O Registers
13.9.2 Keyboard Interrupt Enable Register The keyboard interrupt enable register enables or disables each port A pin to operate as a keyboard interrupt pin.
Address: $0017 Bit 7 Read: KBIE7 Write: Reset: 0 0 0 0 0 0 0 0 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 6 5 4 3 2 1 Bit 0
Figure 13-3. Keyboard Interrupt Enable Register (KBIER) KBIE7-KBIE0 -- Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = PTAx pin enabled as keyboard interrupt pin 0 = PTAx pin not enabled as keyboard interrupt pin
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Keyboard Interrupt Module (KBI)
Technical Data 195
Keyboard Interrupt Module (KBI)
Technical Data 196 Keyboard Interrupt Module (KBI)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Technical Data -- MC68HC08JB1
Section 14. Computer Operating Properly (COP)
14.1 Contents
14.2 14.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
14.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.4.1 OSCXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.4.2 STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.4.3 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.4.4 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 14.4.5 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 14.4.6 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 14.4.7 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 14.4.8 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . 200 14.5 14.6 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 14.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 14.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
14.2 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG register.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Computer Operating Properly (COP)
Technical Data 197
Computer Operating Properly (COP) 14.3 Functional Description
Figure 14-1 shows the structure of the COP module.
SIM OSCXOUT 12-BIT SIM COUNTER SIM RESET CIRCUIT RESET STATUS REGISTER
CLEAR STAGES 5-12
CLEAR ALL STAGES
INTERNAL RESET SOURCES(1) RESET VECTOR FETCH COPCTL WRITE
COP CLOCK COP MODULE 6-BIT COP COUNTER COPEN (FROM SIM) COPD (FROM CONFIG) RESET COPCTL WRITE COP RATE SEL (COPRS FROM CONFIG) NOTE: 1. See SIM section for more details. CLEAR COP COUNTER
Figure 14-1. COP Block Diagram The COP counter is a free-running 6-bit counter preceded by a 12-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 218 - 24 or 213 - 24 OSCXCLK cycles, depending on the state of the COP rate select bit, COPRS in the configuration register. With a 218 - 24 OSCXCLK cycle overflow option (COPRS = 0), a 12MHz OSCXCLK clock (6MHz crystal) gives a COP timeout period of 21.84 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12 through 5 of the SIM counter.
Technical Data 198 Computer Operating Properly (COP)
COP TIMEOUT
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Computer Operating Properly (COP) I/O Signals
NOTE:
Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low for 32 OSCXCLK cycles and sets the COP bit in the reset status register (RSR).
NOTE:
Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly.
14.4 I/O Signals
The following paragraphs describe the signals shown in Figure 14-1.
14.4.1 OSCXCLK OSCXCLK is the clock doubler output signal. OSCXCLK frequency is double of the crystal frequency.
14.4.2 STOP Instruction The STOP instruction clears the COP prescaler.
14.4.3 COPCTL Write Writing any value to the COP control register (COPCTL) (see 14.5 COP Control Register) clears the COP counter and clears bits 12 through 5 of the SIM counter. Reading the COP control register returns the low byte of the reset vector.
14.4.4 Power-On Reset The power-on reset (POR) circuit in the SIM clears the COP prescaler 4096 OSCXCLK cycles after power-up.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Computer Operating Properly (COP)
Technical Data 199
Computer Operating Properly (COP)
14.4.5 Internal Reset An internal reset clears the SIM counter and the COP counter.
14.4.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 14.4.7 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG). 14.4.8 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register (CONFIG).
Address: $001F Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 URSTD LVID SSREC COPRS STOP COPD 5 4 3 2 1 Bit 0
= Unimplemented
Figure 14-2. Configuration Register (CONFIG) COPRS -- COP Rate Select Bit COPRS selects the COP timeout period. Reset clears COPRS. 1 = COP timeout period is (213 - 24) x OSCXOUT cycles 0 = COP timeout period is (218 - 24) x OSCXOUT cycles COPD -- COP Disable Bit COPD disables the COP module. 1 = COP module disabled 0 = COP module enabled
Technical Data 200 Computer Operating Properly (COP) MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Computer Operating Properly (COP) COP Control Register
14.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector.
Address: $FFFF Bit 7 Read: Write: Reset: 6 5 4 3 2 1 Bit 0
Low byte of reset vector Clear COP counter Unaffected by reset
Figure 14-3. COP Control Register (COPCTL)
14.6 Interrupts
The COP does not generate CPU interrupt requests.
14.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby modes.
14.7.1 Wait Mode The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine.
14.7.2 Stop Mode Stop mode turns off the OSCXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Computer Operating Properly (COP)
Technical Data 201
Computer Operating Properly (COP)
The STOP bit in the configuration register (CONFIG) enables the STOP instruction. To prevent inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit.
Technical Data 202 Computer Operating Properly (COP)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Technical Data -- MC68HC08JB1
Section 15. Low Voltage Inhibit (LVI)
15.1 Contents
15.2 15.3 15.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 LVI Control Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . 204
15.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 15.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 15.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
15.2 Introduction
This section describes the low-voltage inhibit module (LVI), which monitors the voltage on the VDD pin and generates a reset when the VDD voltage falls to the LVI trip (VLVR) voltage.
15.3 Functional Description
Figure 15-1 shows the structure of the LVI module. The LVI is enabled after a reset. The LVI module contains a bandgap reference circuit and comparator. Setting LVI disable bit (LVID) disables the LVI to monitor VDD voltage. The LVI module generates one output signal: LVI Reset -- an reset signal will be generated to reset the CPU when VDD drops to below the set trip point.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Low Voltage Inhibit (LVI)
Technical Data 203
Low Voltage Inhibit (LVI)
VDD
LVID
LOW VDD DETECTOR
VDD > VLVR = 0 VDD < VLVR = 1
LVI RESET
Figure 15-1. LVI Module Block Diagram
15.4 LVI Control Register (CONFIG)
Address: $001F Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 0 6 0 URSTD LVID SSREC COPRS STOP COPD 5 4 3 2 1 Bit 0
One-time writable register after each reset. URSTD and LVID bits are reset by POR or LVI reset only.
= Unimplemented
Figure 15-2. Configuration Register (CONFIG) LVID --Low Voltage Inhibit Disable Bit 1 = Low voltage inhibit disabled 0 = Low voltage inhibit enabled
15.5 Low-Power Modes
The STOP and WAIT instructions put the MCU in low-power consumption standby modes. 15.5.1 Wait Mode The LVI module, when enabled, will continue to operate in WAIT Mode. 15.5.2 Stop Mode The LVI module, when enabled, will continue to operate in STOP Mode.
Technical Data 204 Low Voltage Inhibit (LVI) MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Technical Data -- MC68HC08JB1
Section 16. Electrical Specifications
16.1 Contents
16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .206 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 207 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 208 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 USB DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 210
16.10 USB Low-Speed Source Electrical Characteristics . . . . . . . . 211 16.11 USB Signaling Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 16.12 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . . 212
16.2 Introduction
This section contains electrical and timing specifications.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Electrical Specifications
Technical Data 205
Electrical Specifications 16.3 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it.
NOTE:
This device is not guaranteed to operate properly at the maximum ratings. Refer to 16.6 DC Electrical Characteristics for guaranteed operating conditions.
Characteristic(1) Supply voltage Input voltage PTE4/D-, PTE3/D+ RST, IRQ Others Mode entry voltage, IRQ pin Maximum current per pin excluding VDD and VSS Storage temperature Maximum current of PTD0/1 pin Maximum current out of VSS Maximum current into VDD
NOTES: 1. Voltages referenced to VSS
Symbol VDD
Value -0.3 to +6.0 VSS -1.0 to VDD +0.3 VSS -0.3 to VDD +0.3 VSS -0.3 to VREG +0.3 VSS -0.3 to +11 25 -55 to +150 -25 to +50 100 100
Unit V
VIN
V
VDD +VHI
V mA C mA mA mA
I TSTG IOL IMVSS IMVDD
NOTE:
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the range VSS (VIN or VOUT) VREG. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VREG).
Technical Data 206 Electrical Specifications
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Electrical Specifications Functional Operating Range
16.4 Functional Operating Range
Characteristic Operating temperature range Operating voltage range Symbol TA VDD Value 0 to 70 4.0 to 5.5 Unit C V
16.5 Thermal Characteristics
Characteristic Thermal resistance 20-pin PDIP 20-pin SOIC I/O pin power dissipation Power dissipation(1) Constant(2) Average junction temperature Maximum junction temperature Symbol JA PI/O PD K TJ TJM Value 70 70 User-Determined PD = (IDD x VDD) + PI/O = K/(TJ + 273 C) PD x (TA + 273 C) + PD2 x JA TA + (PD x JA) 100 Unit C/W W W
W/C C C
NOTES: 1. Power dissipation is a function of temperature. 2. K is a constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and TJ can be determined for any value of TA.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Electrical Specifications
Technical Data 207
Electrical Specifications 16.6 DC Electrical Characteristics
Characteristic(1) Regulator output voltage Output high voltage (ILoad = -2.0 mA) PTA0-PTA7, PTC0, PTD0/1, PTE1, PTE3, PTE4 Output low voltage (ILoad = 1.6 mA) All I/O pins (ILoad = 50 mA) PTD0/1 in ILDD mode (ILoad = 10 mA) PTE4-PTE3 with USB disabled Input high voltage All ports, OSC1 IRQ, RST Input low voltage All ports, OSC1 IRQ, RST VDD supply current, VDD = 5.25V, fOP = 3MHz Run, with low speed USB(3) Run, with USB suspended(3) Wait, with low speed USB(4) Wait, with USB suspended(4) Stop(5) 0 C to 70 C I/O ports Hi-Z leakage current Input current Capacitance Ports (as input or output) POR re-arm voltage(6) POR rise-time ramp rate(7) Monitor mode entry voltage Pullup resistors Port A, port C, RST, IRQ PTE4-PTE3 with USB module disabled D- with USB module enabled LVI reset LVI reset recover RAM data retention voltage -- -- -- -- -- IIL IIN COut CIn VPOR RPOR VDD+VHI RPU VLVR VLVRR VRDR -- -- -- -- 0 0.035 1.4 x VDD 25 4 1.2 -- -- 2.0 40 5 1.5 3.3 3.5 -- 2.5 2.2 2.2 2.0 300 -- -- -- -- -- -- 5.5 5.0 4.5 4.0 350 10 1 12 8 100 -- 8 55 6 2.0 -- -- -- mA mA mA mA A A A pF mV V/ms V Symbol VREG VOH Min 3.0 VREG -0.8 Typ(2) 3.3 -- Max 3.6 -- Unit V V
VOL
-- -- -- 0.7 x VREG 0.7 x VDD VSS VSS
-- -- -- -- -- -- --
0.4 0.5 0.4 VREG VDD 0.3 x VREG 0.3 x VDD
V
VIH
V
VIL
V
IDD
k
V V V
NOTES: 1. VDD = 4.0 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only.
Technical Data 208 Electrical Specifications
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Electrical Specifications Control Timing
3. Run (operating) IDD measured using external square wave clock source (fXCLK = 6 MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fXCLK = 6 MHz); all inputs 0.2 V from rail; no dc loads; less than 100 pF on all outputs. CL = 20 pF on OSC2; 15 k 5% termination resistors on D+ and D- pins; all ports configured as inputs; OSC2 capacitance linearly affects wait IDD 5. STOP IDD measured with USB in suspend mode; OSC1 grounded; transceiver pullup resistor of 1.5 k 5% between VREG and D- and 15 k 5% termination resistors on D+ and D- pins; no port pins sourcing current. 6. Maximum is highest voltage that POR is guaranteed. 7. If minimum VREG is not reached before the internal POR reset is released, RST must be driven low externally until minimum VREG is reached.
16.7 Control Timing
Characteristic(1) Internal operating frequency(2) RST input pulse width low(3) Symbol fOP tIRL Min -- 125 Max 3 -- Unit MHz ns
NOTES: 1. VDD = 4.0 to 5.5 Vdc; VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD, unless otherwise noted. 2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this information. 3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
16.8 Oscillator Characteristics
Characteristic Crystal frequency(1) External clock Reference frequency(1), (2) Crystal load capacitance(3) Crystal fixed capacitance(3) Crystal tuning capacitance(3) Feedback bias resistor Series resistor(3), (4) Symbol fXCLK fXCLK CL C1 C2 RB RS Min 1 dc -- -- -- -- -- Typ -- -- -- 2 x CL 2 x CL 10 M -- Max 6 6 -- -- -- -- -- Unit MHz MHz
NOTES: 1. The USB module is designed to function at fXCLK = 6 MHz. 2. No more than 10% duty cycle deviation from 50% 3. Consult crystal vendor data sheet 4. Not required for high-frequency crystals
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Electrical Specifications
Technical Data 209
Electrical Specifications 16.9 USB DC Electrical Characteristics
Characteristic(1) Hi-Z state data line leakage Voltage input high (driven) Voltage input high (floating) Voltage input low Differential input sensitivity Differential common mode range Static output low Static output high Output signal crossover voltage Regulator bypass capacitor Regulator bulk capacitor Symbol ILO VIH VIHZ VIL VDI VCM VOL VOH VCRS
CREGBYPASS
Conditions 0 VMin -10 2.0 2.7
Typ
Max +10
Unit A V
3.6 0.8
V V V
|(D+) - (D-)| Includes VDI Range RL of 1.425 K to 3.6 V RL of 14.25 K to GND
0.2 0.8 2.5 0.3 2.8 1.3 -- 0.1 4.7 3.6 2.0
V V V V F F
CREGBULK
NOTES: 1. VDD = 4.0 to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
Technical Data 210 Electrical Specifications
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Electrical Specifications USB Low-Speed Source Electrical Characteristics
16.10 USB Low-Speed Source Electrical Characteristics
Characteristic(1) Internal operating frequency Transition time(2) Rise time Fall time Symbol fOP Conditions -- Min -- Typ 3 Max -- Unit MHz
tR tF tRFM tDRATE
CL = 200 pF CL = 600pF CL = 200 pF CL = 600pF tR/tF 1.5 Mbs 1.5% CL = 600 pF Measured at crossover point CL = 600 pF Measured at crossover point Measured at crossover point Measured at crossover point
75 75
-- 300 -- 300 ns
Rise/Fall time matching Low speed data rate Source differential driver jitter To next transition For paired transitions Receiver data jitter tolerance To next transition For paired transitions Source SEO interval of EOP Source jitter for differential transition to SE0 transition(3) Receiver SEO interval of EOP Must reject as EOP Must accept Width of SEO interval during differential transition
80 1.4775 676.8 -25 -10
-- 1.500 666.0 -- --
120 1.5225 656.8 25 10
% Mbs ns ns
tDDJ1 tDDJ2 tDJR1 tDJR2 tLEOPT
-75 -45 1.25
-- -- -- 667
75 45 1.50
ns
s ns
tLEOPR1 tLEOPR2 tLST
Measured at crossover point Measured at crossover point
210 670 --
-- -- --
-- -- 210
ns
ns
NOTES: 1. All voltages are measured from local ground, unless otherwise specified. All timings use a capacitive load of 50 pF, unless otherwise specified. Low-speed timings have a 1.5k pullup to 2.8 V on the D- data line. 2. Transition times are measured from 10% to 90% of the data signal. The rising and falling edges should be smoothly transitioning (monotonic). Capacitive loading includes 50 pF of tester capacitance. 3. The two transitions are a (nominal) bit time apart.
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Electrical Specifications
Technical Data 211
Electrical Specifications 16.11 USB Signaling Levels
Signaling Levels Bus State Transmit Differential 1 Differential 0 Single-ended 0 (SE0) Data J state (low speed) Data K state (low speed) Idle state (low speed) Resume state Start of packet (SOP) End of packet (EOP) Reset D+ > VOH (min) and D- < VOL (max) D- > VOH (min) and D- < VOL (max) D+ and D- < VOL (max) Differential 0 Differential 1 NA Differential 1 Data lines switch from Idle to K State SE0 for approximately 2 bit times(1) followed by a J state for 1 bit time NA SE0 for 1 bit time(2) followed by a J state for 1 bit time D+ and D- < VIL (max) for 8s Receive (D+) - (D-) > 200 mV (D-) - (D+) > 200 mV D+ and D- < VIL (max) Differential 0 Differential 1 D- > VIHZ (min) and D+ < VIL (max) Differential 1
NOTES: 1. The width of EOP is defined in bit times relative to the speed of transmission. 2. The width of EOP is defined in bit times relative to the device type receiving the EOP. The bit time is approximate.
16.12 TImer Interface Module Characteristics
Characteristic Input capture pulse width Input clock pulse width Symbol tTIH, tTIL tTCH, tTCL Min 1/fOP (1/fOP) + 5ns Max -- -- Unit
Technical Data 212 Electrical Specifications
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
Technical Data -- MC68HC08JB1
Section 17. Mechanical Specifications
17.1 Contents
17.2 17.3 17.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 20-Pin Dual In-Line Package (PDIP) . . . . . . . . . . . . . . . . . . .214 20-Pin Small Outline Integrated Circuit (SOIC) . . . . . . . . . . . 214
17.2 Introduction
This section gives the dimensions for: * * 20-pin plastic dual in-line package (case #738) 20-pin small outline integrated circuit package (case #751D)
MC68HC08JB1 -- Rev. 2.0 MOTOROLA Mechanical Specifications
Technical Data 213
Mechanical Specifications 17.3 20-Pin Dual In-Line Package (PDIP)
-A-
20 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
B
1 10
C
L
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
Figure 17-1. 20-Pin PDIP (Case #738)
17.4 20-Pin Small Outline Integrated Circuit (SOIC)
-A-
20 11
-B-
1 10
10X
P 0.010 (0.25)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
20X
D
M
0.010 (0.25)
TA
S
B
J
S
F R X 45 _ C -T-
18X SEATING PLANE
G
K
M
Figure 17-2. 20-Pin SOIC (Case #751D)
Technical Data 214 Mechanical Specifications
MC68HC08JB1 -- Rev. 2.0 MOTOROLA
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